Abstract: A process for removing skew across a set of at least two clients that are members of a particular trunk, the skew removed from a data path from a first communications system component to a second communications system component. The process using a deskew marker to initiate storage of a set of idle primitives in a FIFO for client member of the particular trunk. Releasing in lockstep, idle primitives for the set of FIFO for the set of client members of the particular trunk after receipt of the final deskew marker. Continuing to route subsequent data for the set of clients for that particular trunk through the set of FIFO for the set of clients for that particular trunk. The data path from the first communications system component to the second communications system component may include traversing a fiber optic network.

Abstract: A process for removing skew across a set of at least two clients that are members of a particular trunk, the skew removed from a data path from a first communications system component to a second communications system component. The process using a deskew marker to initiate storage of a set of idle primitives in a FIFO for client member of the particular trunk. Releasing in lockstep, idle primitives for the set of FIFO for the set of client members of the particular trunk after receipt of the final deskew marker. Continuing to route subsequent data for the set of clients for that particular trunk through the set of FIFO for the set of clients for that particular trunk.

Abstract: A switch (14) that transfers a packet (264) includes a plurality of ports (28) and a switch control system (63) that is electrically connected to the ports (28) and that controls the flow of data through the switch (14). The packet (264) includes a destination vector (215) having one or more original destinations (268). The switch control system (63) receives the destination vector (215) and allows the destination vector (215) to be dynamically updated. For example, the control system (63) can allow the destination vector to be dynamically updated during the transmission of the packet to the one or more original destinations (268). The control system (63) can allow one or more added destinations (268B) to be added to the destination vector (215) and/or the control system (63) can allow one or more of the original destinations (268) to be removed from the destination vector (215) with minimal, if any, influence on performance.

Abstract: A device (212) that transfers data includes a destination (216), a first data source (216), a second data source (216), a connector (220), and a control system (214). The first data source (216) can have first data to send to the destination (216). The second data source (216) can have second data to send to the destination (216). The connector (220) electrically connects the data sources (216) to the destination (216). The device control system (214) is electrically connected to the sources (216) and the destination (216). The device control system (214) utilizes an arbitration progression that sequentially grants access to the connector (220) to only the data sources (216) that have data to send to the destination (216). The device control system (214) can evaluate a first data rate of the first data and a second data rate of the second data, and can grant access to the data sources (216) that have data to send to the destination (216).

Abstract: A data switch (14) for transferring data includes an A port group (34A), a B port group (34B), and an AB connector (52). The A port group (34A) includes an A interface (44), a first A port (36) that is electrically connected to the A interface (44), and a second A port (36) that is electrically connected to the A interface (44). The B port group (34B) includes a B interface (46), a first B port (38) that is electrically connected to the B interface (46), and a second B port (38) that is electrically connected to the B interface (46). The AB connector (52) directly connects the A interface (44) to the B interface (46) so that data from first A port (36) is transferred from the A interface (44) to the B interface (46) via the AB connector (52). Additionally, the data switch (14) includes switching algorithms that control the transfer of data packets between the ports (36)-(42). The switching algorithms can transfer the data packets in a burst fashion.

Abstract: A grid array microelectronic package includes a substrate and an array of external connectors on the substrate that are arranged in rows and columns to define a periphery of the array and the interior of the array. A routing channel is provided in the array that increases the periphery of the array by at least four external connectors, compared to absence of the routing channel. The routing channel may be made of two missing external connectors, at least two strapped external connectors and/or at least two “no-connect” external connectors in the array that extend from the periphery of the array towards the interior of the array. Signal conductors may extend along the routing channel.

Abstract: A First-In-First-Out (FIFO) memory device includes a FIFO memory block, a data input interface that writes data into the FIFO memory block in synchronization with a first clock, and a data output interface that reads the data from the FIFO memory block in synchronization with a second clock. The data input interface provides a first indication to the data output interface that the received data has been written into the FIFO memory block. The first indication persists until reset by the data output interface. The data output interface provides a second indication to the data input interface that the received data has been read from the FIFO memory block. The second indication persists until reset by the data input interface.

Abstract: Preferred memory devices include a first bit line within a first block of memory and a second bit line within a second block of memory. The first bit line is electrically coupled to a reference voltage signal line by a pull-up transistor that turns on in response to an active first bit line pull-up signal (e.g., /BLPU_IOn=0). The second bit line is also electrically coupled to the reference voltage signal line by a pull-up transistor that turns on in response to an active second bit line pull-up signal (e.g., /BLPU_IOn+1=0). A control circuit is provided and this control circuit is responsive to a multi-bit shift signal. The control circuit disables generation of the active first bit line pull-up signal in favor of an active second bit line pull-up signal when a value of the shift signal designates replacement of the first block of memory with the second block of memory.

Abstract: A priority encoding interface transmits data to the receiving device from a highest priority FIFO memory block that is selected from at least two of a plurality of FIFO memory blocks until the highest priority FIFO memory block is empty. The interface inhibits transfer of data to the data receiving device from remaining ones of the FIFO memory blocks, until the highest priority FIFO memory block is empty. Transmission of data from the highest priority FIFO memory block and inhibited transfer of data from remaining ones of the FIFO memory blocks, take place in response to an indication from the data receiving device that the data receiving device is enabled to receive data from the at least two of the FIFO memory blocks.

Abstract: Described is a last stage decoder that generates a local word line signal within a bank of a single-ported memory cell array structure. The decoder inputs predecoded global row address signals, as well as predecoded local row address signals. In order to generate the local word line signal, and thus access a memory cell within a given bank, both one predecoded global row address signal, as well as one predecoded local row address signal must be present. The predecoded local row address signal turns on a pass gate transistor, and allows the predecoded global row address signal to pass through the pass gate transistor and create the local word line signal.