Abstract: A self-aligned bipolar structure for use on SOI (silicon on insulator) substrates is described. This structure does not require etching poly and stopping on single crystal silicon. This is also a process of forming a MOS transistor and a vertical, fully self-aligned bipolar transistor on an insulating substrate.

Abstract: The described embodiments of the present invention provide structures and methods for fabricating the structures which provide compact contact from the surface of an integrated circuit to a buried layer formed in conjunction with a vertical gate extending from the buried layer to a doped layer at a surface of the integrated circuit. In one embodiment, trenches are simultaneously formed for providing the vertical gate and the contact to the buried layer. A thermal oxide layer is formed on the surface of the integrated circuit to provide an insulating layer on the surfaces of both the contact trench and the gate trench. A first layer of in situ doped polycrystalline silicon is deposited on the surface of the integrated circuit. The thickness of this polycrystalline silicon layer is chosen so as to not fill the gate and contact trenches. A masking layer is then provided to protect the gate trench and expose the contact trench.

Abstract: Disclosed is a scaled, self aligned, bipolar transistor and a method of fabrication which is compatible with MOSFET device structures. A transistor intrinsic base region is formed in the face of an isolated epitaxial region and polysilicon is deposited, patterned and etched to form emitter regions. An oxide cap and first sidewall oxide spacers are formed on the polysilicon emitters and the single crystal silicon is etched using the oxide covered emitters as a mask to form recessed regions in the epitaxial layer. The extrinsic base region is then formed adjacent at least one side of the base by implanting appropriate dopants into one of the recessed regions. A second sidewall oxide spacer is then formed on the vertical base emitter structure and a heavily doped collector contact region is formed by implanting appropriate dopants into another one of the recessed silicon regions.

Abstract: The invention provides a bipolar transistor structure on a buried oxide layer for use in an integrated circuit and a method for fabricating the same. The invention may be incorporated into a method for fabricating bipolar transistors in a BiCMOS structure. The bipolar transistor is constructed in two stacked epitaxial layers. The first epitaxial layer is used to form both the MOSFET and the buried collector of the bipolar transistor. The second epitaxial layer is grown as a blanket epitaxial layer. The intrinsic collector and the base of the bipolar transistor are formed in the second epitaxial layer. An oxide layer is formed over the base. The emitter is formed of a polysilicon layer which is deposited through an opening in the oxide layer such that the polysilicon layer contacts the second epitaxial layer.

Abstract: A bipolar transistor and method of making the same is disclosed. The transistor has an emitter region which is diffused from polysilicon into the intrinsic base region, where the polysilicon is doped with two dopant species of different diffusivity. The impurity concentration of the higher diffusivity species, for example phosphorous, can be selected to define the emitter junction depth, which is preferably shallow, while the impurity concentration of the lower diffusivity species, for example arsenic, can be selected to provide a high conductivity emitter electrode, as well as reduce the sensitivity of the emitter electrode to counterdoping from the implantation of the extrinsic base region. The structure is compatible with BiCMOS processing, as the same anneal can be used to diffuse the emitter and the source/drains of the MOS transistors, with the emitter junction depth optimized via the implant conditions of the higher diffusivity species.

Abstract: The described embodiments of the present invention provide a protective layer on the surface of silicided regions and methods for its formation. In the primary described embodiment, a titanium silicide layer is formed in integrated circuitry using self-aligned techniques. Local interconnection layers may be formed using biproducts of the self-aligned titanium disilicide formation. A layer of another siliciding metal, for example platinum, is then formed overall. The platinum layer is then subjected to an annealing step which causes a portion of the silicon in the titanium disilicide layers to react with the platinum to form platinum silicide. This platinum silicide layer is formed in a self-aligned manner on the surface of the silicided regions. The platinum silicide layer serves to protect the underlying titanium disilicide layer from subsequent etching steps of other harmful processing operations.

Abstract: A bipolar transistor with a subcollector diffused from a trench contact is disclosed. The bipolar transistor is formed by an n-type collector region disposed over a p-type substrate, or over a p-type epitaxial layer disposed over a p+ substrate. A trench is formed surrounding the transistor, with a dielectric layer formed on the sides and bottom of the trench. An opening is formed in the dielectric layer adjacent the collector region; the trench is filled with a dopant source such as heavily doped n-type polysilicon. During the diffusion of the base region from an implant, n-type dopant diffuses out from the filled trench through the opening, to form an n+ subcollector in the collector region. An emitter region, and an extrinsic base region, are then formed to complete the transistor. Additional disclosed embodiments include the use of an isolation structure to fill the trench on the side of the transistor adjacent the extrinsic base, so that collector-to-base capacitance is minimized.

Abstract: Disclosed is a scaled, self aligned, bipolar transistor and a method of fabrication which is compatible with MOSFET device structures. A transistor intrinsic base region is formed in the face of an isolated epitaxial region and polysilicon is deposited, patterned and etched to form emitter regions. An oxide cap and first sidewall oxide spacers are formed on the polysilicon emitters and the single crystal silicon is etched using the oxide covered emitters as a mask to form recessed regions in the epitaxial layer. The extrinsic base region is then formed adjacent at least one side of the base by implanting appropriate dopants into one of the recessed regions. A second sidewall oxide spacer is then formed on the vertical base emitter structure and a heavily doped collector contact region is formed by implanting appropriate dopants into another one of the recessed silicon regions.

Abstract: A resistor (10) includes a resistive filling (28) formed within a trench (12) and separated therefrom by an insulating layer (26). Resistive filling (28) is of the same type of semiconductor material as that of second layer (22), but of an opposite extreme of dopant concentration. A head region (32) may be formed below interface (30) within second layer (22) to more clearly delineate the edge of resistive filling (28) from second layer (22). Where resistive filling (28) is of a low dopant concentration, low resistance contact region (34) is formed of a high dopant concentration in order to provide a minimum resistance contact to resistive filling (28).

Abstract: A process for fabricating an integrated circuit with both bipolar and CMOS transistors is disclosed. Buried n-type and p-type layers are diffused into a substrate, and a substantially intrinsic epitaxial layer is formed above the buried layers. N-wells and p-wells are formed into the epitaxial layer self-aligned relative to one another, over their respective buried layers. The intrinsic epitaxial layer allows the formation of the p-well, into which n-channel MOS transistors are eventually formed, with minimal mobility degradation due to counterdoping. Isolation oxide regions are formed at the boundaries of the wells, for isolation of the wells relative to one another. Trench isolation may alternatively be used, such trenches including polysilicon plugs which are recessed into the trench, and filled with an oxide layer to allow the placement of contacts over the trench with minimal overetch-induced or stress-induced leakage.

Abstract: Disclosed is a scaled, self aligned, bipolar transistor and a method of fabrication which is compatible with MOSFET device structures. A transistor intrinsic base region is formed in the face of an isolated epitaxial region and polysilicon is deposited, patterned and etched to form emitter regions. An oxide cap and first sidewall oxide spacers are formed on the polysilicon emitters and the single crystal silicon is etched using the oxide covered emitters as a mask to form recessed regions in the epitaxial layer. The extrinsic base region is then formed adjacent at least one side of the base by implanting appropriate dopants into one of the recessed regions. A second sidewall oxide spacer is then formed on the vertical base emitter structure and a heavily doped collector contact region is formed by implanting appropriate dopants into another one of the recessed silicon regions.

Abstract: A Schottky diode (12) whose fabrication is adapted to a CMOS process is disclosed. The Schottky diode (12) is formed in an N- well (24). A spacer (40) is formed over the N- well (24), then an N+ region (52) is implanted along one side of the spacer (40). The spacer (40) is structurally similar to a CMOS transistor (14, 16) gate structure (38), and the N+ implantation process is the same one which is used to implant N+ source and drain regions (53) in an NMOS transistor (16). A guard ring (60) is implanted using the same process steps which are used to implant source and drain regions (56) for a PMOS transistor (14). A silicide (62) contacts the N- well region (24) along an opposing side of the spacer (40) to form a rectifying junction. This silicide (62) is additionally used in the CMOS transistors (14, 16) to lower contact resistance in conductive semiconductor regions (38, 53, and 56).

Abstract: A method of forming trench isolation is disclosed. A trench is etched, either through field oxide or not, into the substrate, using an oxide hard mask. Implant of a channel-stop is then performed through a dummy sidewall oxide, followed by stripping of the dummy oxide and regrowth of the sidewall oxide. A polysilicon layer is deposited into the trench and over the wafer, and is etched to clear from the surface, and overetched so that a recess is formed within the trench. The recess is then filled with a TEOS oxide layer deposited over the wafer surface, and the deposited oxide at the top of the trench is planarized with the surrounding surface.

Abstract: The preferred embodiments include Schottky barrier diode (80) clmaped bipolar transistors for use in planar integrated circuits with the diode (80) being formed in a trench to increase junction area, reduce series resistance from junction to the buried layer (64), and reduce lateral extent of the extrinsic base (78).

Abstract: Refractory metals, refractory metal silicide, and polysilicon/refractory metal silicide sandwich structures integrated circuits are etched using carbonyl chemistry. That is, the deposited material is plasma etched using an etchant gas mixture which contains a gas, such as CO2, which can dissociate to provide carbonyl groups (CO) or, in combination with halogen sources, carbonyl halide radicals.