Patents by Inventor Robert Hölzl

Robert Hölzl has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9242867
    Abstract: The invention provides polycrystalline silicon having concentrations of dopants of 1-10 ppta of boron, 1-20 ppta of phosphorus, 1-10 ppta of arsenic, 0.01-1 ppta of aluminum, and having a charge carrier lifetime of at least 2000 and at most 4500 ?s.
    Type: Grant
    Filed: December 12, 2012
    Date of Patent: January 26, 2016
    Assignee: Wacker Chemie AG
    Inventors: Robert Baumann, Robert Hoelzl, Michael Weichselgartner
  • Patent number: 7820549
    Abstract: Semiconductor wafers with a diameter of at least 200 mm comprise a silicon carrier wafer, an electrically insulating layer and a semiconductor layer located thereon, the semiconductor wafer having been produced by means of a layer transfer process comprising at least one RTA step, wherein the semiconductor wafer has a warp of less than 30 ?m, a DeltaWarp of less than 30 ?m, a bow of less than 10 ?m and a DeltaBow of less than 10 ?m. Processes for the production of a semiconductor wafer of this type require specific heat treatment regimens.
    Type: Grant
    Filed: January 31, 2008
    Date of Patent: October 26, 2010
    Assignee: Siltronic AG
    Inventors: Markus Blietz, Robert Hoelzl, Reinhold Wahlich, Andreas Huber
  • Patent number: 7537657
    Abstract: A process for producing a single-crystal silicon wafer, comprises the following steps: producing a layer on the front surface of the silicon wafer by epitaxial deposition or production of a layer whose electrical resistance differs from the electrical resistance of the remainder of the silicon wafer on the front surface of the silicon wafer, or production of an external getter layer on the back surface of the silicon wafer, and heat treating the silicon wafer at a temperature which is selected to be such that an inequality (1) [ Oi ] < [ Oi ] eq ? ( T ) ? exp ? 2 ? ? SiO ? ? 2 ? ? rkT is satisfied, where [Oi] is an oxygen concentration in the silicon wafer, [Oi]eq(T) is a limit solubility of oxygen in silicon at a temperature T, ?SiO2 is the surface energy of silicon dioxide, ? is a volume of a precipitated oxygen atom, r is a mean COP and k the Boltzmann constant, with the silicon wafer, during the heat treatment, at least part of the time being exposed to an oxygen-con
    Type: Grant
    Filed: June 29, 2006
    Date of Patent: May 26, 2009
    Assignee: Siltronic AG
    Inventors: Christoph Seuring, Robert Hoelzl, Reinhold Wahlich, Wilfried Von Ammon
  • Patent number: 7407891
    Abstract: Semiconductor wafers are leveled by position-dependent measurement of a wafer-characterizing parameter to determine the position-dependent value of this parameter over an entire surface of the semiconductor wafer, etching the entire surface of the semiconductor wafer simultaneously under the action of an etching medium with simultaneous illumination of the entire surface, the material-removal etching rate dependent on the light intensity at the surface of the semiconductor wafer, the light intensity being established in a position-dependent manner such that the differences in the position-dependent values of the parameter measured in step a) are reduced by the position-dependent material-removal rate. Semiconductor wafers with improved flatness and nanotopography, and SOI wafers with improved layer thickness homogeneity are produced by this process.
    Type: Grant
    Filed: November 7, 2005
    Date of Patent: August 5, 2008
    Assignee: Siltronic AG
    Inventors: Theresia Bauer, Robert Hoelzl, Andreas Huber, Reinhold Wahlich
  • Publication number: 20080122043
    Abstract: Semiconductor wafers with a diameter of at least 200 mm comprise a silicon carrier wafer, an electrically insulating layer and a semiconductor layer located thereon, the semiconductor wafer having been produced by means of a layer transfer process comprising at least one RTA step, wherein the semiconductor wafer has a warp of less than 30 ?m, a DeltaWarp of less than 30 ?m, a bow of less than 10 ?m and a DeltaBow of less than 10 ?m. Processes for the production of a semiconductor wafer of this type require specific heat treatment regimens.
    Type: Application
    Filed: January 31, 2008
    Publication date: May 29, 2008
    Applicant: SILTRONIC AG
    Inventors: Markus Blietz, Robert Hoelzl, Reinhold Wahlich, Andreas Huber
  • Patent number: 7235863
    Abstract: A process for producing a single-crystal silicon wafer, comprises the following steps: producing a layer on the front surface of the silicon wafer by epitaxial deposition or production of a layer whose electrical resistance differs from the electrical resistance of the remainder of the silicon wafer on the front surface of the silicon wafer, or production of an external getter layer on the back surface of the silicon wafer, and heat treating the silicon wafer at a temperature which is selected to be such that an inequality (1) [ O ? ? i ] < [ O ? ? i ] eq ? ( T ) ? exp ? ? 2 ? ? SiO ? 2 ? ? r ? ? k ? ? T is satisfied, where [Oi] is an oxygen concentration in the silicon wafer, [Oi]eq(T) is a limit solubility of oxygen in silicon at a temperature T, ?SiO2 is the surface energy of silicon dioxide, ? is a volume of a precipitated oxygen atom, r is a mean COP radius and k the Boltzmann constant, with the silicon wafer, during the heat treatment, at least pa
    Type: Grant
    Filed: July 16, 2004
    Date of Patent: June 26, 2007
    Assignee: Siltronic AG
    Inventors: Christoph Seuring, Robert Hölzl, Reinhold Wahlich, Wilfried Von Ammon
  • Publication number: 20060278157
    Abstract: A process for producing a single-crystal silicon wafer, comprises the following steps: producing a layer on the front surface of the silicon water by epitaxial deposition or production of a layer whose electrical resistance differs from the electrical resistance of the remainder of the silicon wafer on the front surface of the silicon wafer, or production of an external getter layer on the back surface of the silicon wafer, and heat treating the silicon wafer at a temperature which is selected to be such that an inequality (1) [ Oi ] < [ Oi ] eq ? ( T ) ? exp ? 2 ? ? SiO ? ? ? 2 ? ? rkT is satisfied where [Oi] is an oxygen concentration in the silicon wafer, [Oi]eq(T) is a limit colubility of oxygen in silicon at a temperature T, ?sio2 is the surface energy of silicon dioxide, ? is a volume of a precipitated oxygen atom, r is a mean COP and k the Boltzmann constant, with the silicon wafer, during the heat treatment, at least part of the time being exposed to an oxygen-containing
    Type: Application
    Filed: June 29, 2006
    Publication date: December 14, 2006
    Applicant: Siltronic AG
    Inventors: Christoph Seuring, Robert Hoelzl, Reinhold Wahlich, Wilfried Von Ammon
  • Patent number: 7122865
    Abstract: An SOI wafer, includes a substrate made from silicon, an electrically insulating layer with a thermal conductivity of at least 1.6 W/(Km) and a single-crystal silicon layer with a thickness of from 10 nm to 10 ?m, a standard deviation of at most 5% from the mean layer thickness and a density of at most 0.5 HF defects/cm2. A process is for producing an SOI wafer of this type, in which a substrate wafer made from silicon is joined to a donor wafer via a layer of the electrically insulating material which has previously been applied. The donor wafer bears a donor layer of single-crystal silicon, with a concentration of vacancies of at most 1012/cm3 and of vacancy agglomerates of at most 105/cm3. After the wafers have been joined, the thickness of the donor wafer is reduced in such a manner that the single-crystal silicon layer having these properties is formed from the donor layer, this single-crystal silicon layer being joined to the substrate wafer via the layer of electrically insulating material.
    Type: Grant
    Filed: May 25, 2004
    Date of Patent: October 17, 2006
    Assignee: Siltronic AG
    Inventors: Robert Hölzl, Dirk Dantz, Andreas Huber, Ulrich Lambert, Reinhold Wahlich
  • Publication number: 20060097355
    Abstract: Semiconductor wafers are leveled by a) position-dependent measurement of a wafer-characterizing parameter to determine the position-dependent value of this parameter over an entire surface of the semiconductor wafer, b) etching the entire surface of the semiconductor wafer simultaneously under the action of an etching medium with simultaneous illumination of the entire surface, the material-removal etching rate dependent on the light intensity at the surface of the semiconductor wafer, the light intensity being established in a position-dependent manner such that the differences in the position-dependent values of the parameter measured in step a) are reduced by the position-dependent material-removal rate, semiconductor wafers with improved flatness and nanotopography and SOI wafer with improved layer thickness homogeneity are achieved. An apparatus for carrying out the method is also disclosed.
    Type: Application
    Filed: November 7, 2005
    Publication date: May 11, 2006
    Applicant: Siltronic AG
    Inventors: Theresia Bauer, Robert Hoelzl, Andreas Huber, Reinhold Wahlich
  • Publication number: 20060046431
    Abstract: Semiconductor wafers with a diameter of at least 200 mm comprise a silicon carrier wafer, an electrically insulating layer and a semiconductor layer located thereon, the semiconductor wafer having been produced by means of a layer transfer process comprising at least one RTA step, wherein the semiconductor wafer has a warp of less than 30 ?m, a DeltaWarp of less than 30 ?m, a bow of less than 10 ?m and a DeltaBow of less than 10 ?m. Processes for the production of a semiconductor wafer of this type require specific heat treatment regimens.
    Type: Application
    Filed: August 18, 2005
    Publication date: March 2, 2006
    Applicant: Siltronic AG
    Inventors: Markus Blietz, Robert Hoelzl, Reinhold Wahlich, Andreas Huber
  • Patent number: 6803331
    Abstract: A process for the heat treatment of a silicon wafer, during which the silicon wafer is at least temporarily exposed to an oxygen-containing atmosphere, the heat treatment taking place at a temperature which is selected in such a way that the inequality [ Oi ] < [ Oi ] eq ⁢ ( T ) ⁢ exp ⁢ ( 2 ⁢ σ SiO 2 ⁢ Ω rkT ) is satisfied, where [Oi] is the oxygen concentration in the silicon wafer [Oi]eq(T) is the limit solubility of oxygen in silicon at a temperature T, &sgr;SiO2 is the surface energy of silicon dioxide &OHgr; is the volum
    Type: Grant
    Filed: February 4, 2003
    Date of Patent: October 12, 2004
    Assignee: Siltronic AG
    Inventors: Robert Hölzl, Christoph Seuring, Reinhold Wahlich, Wilfried Von Ammon