Abstract: A receiver termination circuit includes an internal AC coupling capacitor and an adjustable resistor forming an adjustable high-pass filter (HPF) at a receiver side of a transmission medium, and a digital-to-analog converter (DAC) coupled to the adjustable HPF, the DAC configured to provide a signal having a low-pass filter response to the adjustable HPF to provide a DC restore function.

Abstract: A receiver termination circuit includes an internal AC coupling capacitor and an adjustable resistor forming an adjustable high-pass filter (HPF) at a receiver side of a transmission medium, and a digital-to-analog converter (DAC) coupled to the adjustable HPF, the DAC configured to provide a signal having a low-pass filter response to the adjustable HPF to provide a DC restore function.

Abstract: A random noise signal generator circuit comprising a random noise source that produces a random noise signal, an amplification circuit that amplifies the random noise signal to produce an amplified random noise signal, a feedback loop having a DC offset correction circuit, and a summer. The DC offset correction circuit processes a fed back portion of the amplified random noise signal to produce a DC offset correction signal. The summer sums the random noise signal produced by the random noise source and the DC offset correction signal to produce a summed signal. The summer is electrically coupled to the amplification circuit for providing the summed signal to the amplification circuitry. The amplification circuitry amplifies the summed signal to produce a random noise output signal.

Abstract: A frequency divider apparatus is a closed loop system of a recirculating memory element, at least one feedback memory element and an end memory element in series combination. Each memory element accepts a common clock. An end memory element output is logically combined with at least one of the other memory element outputs and provides an input to the closed loop system to generate a self-initializing state machine.

Abstract: An apparatus has a frequency divider accepting a clock. The frequency divider is selectable between an N divide factor and an M divide factor via a divide mode signal, where an absolute value of (N?M)=1. The apparatus also has a pulse generator responsive to a slip signal and driven by an output of the frequency divider and providing the divide mode signal to the frequency divider.

Abstract: A method and apparatus for operating a memory is presented. Information is stored in the memory based on a first time domain and information is read from the memory based on a second time domain. A cooperative relationship is maintained between a write pointer which points to memory locations, where data will be stored and a read pointer which points to memory locations, from which data will be read. A FIFO memory is presented which has memory locations and a register array is presented which stores a bit array that has bit locations. Each bit location in the bit array corresponds to a memory location in the memory. As the write pointer points to a memory location and data is stored in the memory location, a bit (e.g. flag) is set in the bit array. The Flag designates whether the data stored in the memory location is available for reading. Prior to reading information from the memory location, a test is made of the bit location that corresponds to the memory location.

Abstract: A method and circuit is presented for generating a random bit stream based on thermal noise of a Complementary Metal Oxide Semiconductor (CMOS) device. A circuit implementing the invention preferably includes at least a pair of identically implemented thermal noise generators whose outputs feed a differential amplifier. The differential amplifier measures and amplifies the difference between the noise signals. A sampling circuit compares the difference with a threshold value that is selected to track with process/voltage/temperature variations of the noise generator circuits to output a binary bit having a bit value determined according to the polarity of the noise difference signal relative to the threshold value. The sampling circuit may be clocked to generate a random bit stream.

Abstract: A series of logic clouds is used to distribute and propagate signals traveling a relatively long distance across a data logic circuit fabric. One or more long distance signals originate from an initial logic cloud that may be located on a source data block and pass through a series of logic clouds that may be located on an intermediate data block before passing through a destination logic cloud located on a destination data block. Each logic cloud reads both stabilized logic signals and long distance signals and employs a NAND gate connected with an inverter to perform not only logical operations but also to act as a repeater between the logic clouds. The stabilized logic signals may represent signals that originate from other sources along a given data path.

Abstract: A method for increasing the effectiveness of the microbicide propiconazole, (RS)-1-2-[(2,4-dichlorophenyl)-2-propyl-1,3-dioxalan-2ylmethyl]-1H-1,2,4-triazole, is described. In the method, propiconazole and a potentiator, an N-alkyl heterocyclic compound, its salt, or a mixture thereof, are applied to a substrate or aqueous system subject to the growth of microorganisms. The N-alkyl heterocyclic compound, its salt, or a mixture thereof is applied in an amount effective to increase the microbicidal activity of the microbicide. The N-alkyl heterocyclic compound has the formula: The variable “n” ranges from 5 to 17, and the heterocyclic ring defined by is a substituted or unsubstituted ring having four to eight members. Microbicidal compositions are described where propiconazole and an N-alkyl heterocyclic compound, its salt, or a mixture thereof are present in a combined amount: effective to control the growth of at least one microorganism.

Abstract: An input number is applied to a look-up table that supplies three coefficients based upon certain bits of the input that define a series of bins. The first coefficient is fed directly to an adder that produces the output. The second coefficient is multiplied by a number corresponding to how far the input is from the edge of a bin. This number is then input to the adder that produces the output. The third coefficient is multiplied by a number that is the result of a curve-fit function of a number corresponding to how far the input is from the middle of a bin. This result is then input to the adder that produces the output. These three addends are aligned and summed to produce an output that corresponds within a certain precision of a chosen mathematical function of the input such as the mathematical inverse (1/x) or the mathematical inverse of the square root of the input.

Abstract: A bit position, M, that determines the accuracy and efficiency of the approximation is selected from an N bit binary number. The multiplicand is generated by removing the Mth bit from the binary number, shifting the bits of lower order than the Mth bit up on position, then filling the lowest order bit with a zero. The multiplier is generated by removing the Mth bit, and all lower order bits from the binary number. Booth's algorithm is then used to multiply the multiplicand and the multiplier except that the Mth bit is used instead of an assumed zero during the first step of the multiplication. In hardware, a partial Booth-encoded multiplier is used to produce and approximate square of a binary number. For an N bit number, and a selected bit in the Mth position, the partial Booth-encoded multiplier has N columns, and N−M rows and N−M booth encoders.

Abstract: A system and method for transferring data between alternately evaluated first and second logic blocks of a dynamic logic pipeline. Associated with the system and method is a transparent data-triggered pipeline latch for controlling data flow between the first and second logic blocks. During an evaluation period accorded the first logic block, data existing at the logic block's data inputs is evaluated. Substantially simultaneously, the data-triggered latch is reset. As valid data is output from the first logic block, the latch is triggered. Immediately after the latch has been triggered, and before a clock-triggered evaluation period is accorded the second logic block, the data stored in the latch is output to the second logic block. Propagation of the early arriving data may be halted by ANDing the early arriving data signals with clocked signals which remain invalid. The invalid signals may comprise clock or data signals.

Abstract: Improved and less complicated leading bit anticipation (LBA) for a PKG floating point adder of n-bit 2's complement operands is accomplished by representing de-normalized (n+1)-bit operands as (n+1)-many PKG symbols. These are grouped into (n-1)-many triples, each of which has two adjacent PKG symbols in common with its neighboring triple. Presuming the existence of a least significant PKG symbol of K allows the formation of an additional triple of lesser significance. Each triple produces an associated transition bit that when set indicates, for the partial summation segment of the raw sum of bit location corresponding to the location of the triple, if the left-most two bits of the corresponding partial summation segment are, or would be with a carry-in, of opposite bit values. The bit position of the most-significant set transition bit is determined in terms of how many bit positions J that is from the most significant transition bit position.

Abstract: A method and apparatus for determining the trailing bit position from a two operand addition is described. The determination of the trailing bit occurs in parallel with the addition. The two operands are encoded together and the encoded word used to determine the trailing bit position. As the operations of encoding the operands and operating upon the encoded operands require no more time than known methods to determine the trailing bit position after the addition is completed, and as the encoding and operating on the encoded words occurs in parallel with the addition operation, the present invention allows faster processing in the floating point unit.

Abstract: An apparatus and method are disclosed for regulating power consumption in a digital system of the kind including at least one triggerable functional block that consumes more power when triggered than when not triggered. In an embodiment for use with a digital system that includes a pipeline of such triggerable functional blocks, a state machine sequentially applies trigger pulses to each of the functional blocks in the pipeline whenever the output of an OR gate is asserted. It does so by generating a series of enable signals that are used to gate a clock signal to the trigger inputs of the functional blocks. The state machine includes a series of storage devices having outputs. Outputs of the storage devices are used to provide the enable signals. The inputs of the OR gate are coupled to a start signal that indicates when the functional blocks should be triggered to process data, and also to a dummy start signal that indicates when the functional blocks should be triggered to maintain power consumption.

Abstract: The operation of a pipeline is observed by launching two or more sets of data into the pipeline on consecutive clock cycles. The clock free-runs for as many cycles as it takes the data to propagate through the stages of the pipeline. The output latches of each stage of the pipeline are only sampled when the data of interest is held in each output latch, respectively. Observation may be completely controlled through a standard test access port (TAP). Observation may be accomplished by halting the clock to scan new data in and results out, or with the clock free-running. The inputs to the pipeline may come from test registers or from circuitry which feeds the pipeline during normal operation.

Abstract: A system and method for improving alpha-particle induced soft error rates in integrated circuits is provided. Logic isolation circuits implemented using a substantially fewer number of pn-junctions are situated at the outputs of fast logic portions containing a substantially greater number of pn-junctions. The present invention reduces the vulnerability of a dynamic logic circuit of incurring alpha soft errors by effectively trading the probability of an isolation circuit composed of only a few pn-junctions incurring alpha-particle strikes with the probability of a fast logic circuit having substantially more pn-junctions incurring alpha-particle strikes. By reducing the number of pn-junctions susceptible to alpha-particle strikes, the present invention significantly lowers the potential alpha-particle induced soft error rate.

Abstract: A system and method for quiescent current testing of dynamic logic circuitry. Nodes shorted to ground are detected during a dynamic pre-charge state. Nodes shorted to a power supply potential are detected by driving all nodes of interest to ground during a dynamic evaluation phase. Nodes of interest are driven to ground directly by one additional transistor per node or indirectly by logical propagation from upstream nodes. As a result, only two current measurements are needed for all shorted node faults, even for pipelined systems with multiple clocks. There is no need for input test signal sequences and no need for signal propagation to outputs for detection. Specific embodiments are provided for single-rail logic, single-rail pipelined systems, dual-rail logic and dual-rail pipelined systems. For single-rail pipelined systems, optional transistors between stages enable preservation of logical states during testing.

Abstract: Clocking systems and methods of the present invention use two or more different clock signals for respective groups or stages of self-timed dynamic (or mousetrap) logic gates. Each clock signal defines a precharging time interval and an evaluation time interval for its respective group or stage of self-timed dynamic logic gates. Using the two or more different clock signals, pipelining of the groups or stages of the self-timed dynamic logic gates can be performed.

Abstract: A rounding means is associated with a carry propagate adder of a floating point processor in order to reduce latency and enhance performance. The rounding mechanism performs a rounding function approximately simultaneously with an addition function performed by the carry propagate adder on fraction inputs FA, FB to ultimately derive a resultant fraction FR, thereby eliminating the need for a conventional post-normalize incrementer. The rounding mechanism has a carry select adder and rounding logic network. The rounding logic network communicates with the carry propagate adder and the carry select adder in order to provide rounding information to the carry select adder. The carry select adder and the rounding logic network jointly provide a rounded output, which is then normalized by the normalizer to thereby derive the resultant fraction.