Patents by Inventor Robert H. Noble

Robert H. Noble has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200138520
    Abstract: A method for designing a patient-customized EA or selecting an existing EA that fits the patient best includes segmenting shapes of SOIs of the cochlea in a pre-operative CT image using a shape model; defining a 3D curve of interest within the shape model of the SOIs as a sequence of points-; automatically transforming the defined 3D curve to the pre-operative CT image so as to obtain a structure curve in the cochlea; determining a length and curvatures of the structure curve at the sequence of points; and designing a patient-customized EA or selecting an existing EA based on the determined length and curvatures of the structure curve such that after the EA shape model, which estimates the resting state shape of the EA, is rigidly registered to the structure curve in the cochlea, the EA shape model has a registration error smaller than a preset value.
    Type: Application
    Filed: April 24, 2018
    Publication date: May 7, 2020
    Inventors: Jack H. NOBLE, Robert F. LABADIE, Benoit M. DAWANT
  • Publication number: 20200139125
    Abstract: A method for using information of patient-specific cochlea size and/or shape to determine a patient-customized cochlear implant electrode insertion and placement plan includes segmenting shapes of structures of interest (SOIs) of the cochlea in a pre-operative CT image of the cochlea using a shape model; defining a 3D modiolar hugging curve within the shape model of the SOIs as a sequence of points; automatically transforming the defined 3D modiolar hugging curve to the pre-operative CT image so as to obtain a modiolar curve in the cochlea; rigidly registering an EA shape model of the EA to the modiolar curve in the cochlea, thereby placing a resting state shape of the EA within the patient's SOIs such that the EA matches the modiolar curve in the cochlea; and determining a patient-customized insertion plan for electrode placement using the registered EA shape model.
    Type: Application
    Filed: April 24, 2018
    Publication date: May 7, 2020
    Inventors: Jack H. NOBLE, Robert F. LABADIE, Benoit M. DAWANT
  • Patent number: 10546388
    Abstract: One aspect of the invention provides a method for customizing cochlear implant stimulation of a living subject. The cochlear implant includes an electrode array having a plurality of electrodes implanted in a cochlea of the living subject. The method includes determining a position for each of the plurality of electrodes and spiral ganglion nerves that the electrode array stimulates, determining a geometric relationship between neural pathways within the cochlea and the electrode array implanted therein, and using one or more electrodes of the electrode array to stimulate a group of SG neural pathways of the cochlea based on the location of the one or more electrodes and their geometric relationship with the neural pathways.
    Type: Grant
    Filed: February 15, 2017
    Date of Patent: January 28, 2020
    Assignee: VANDERBILT UNIVERSITY
    Inventors: Jack H. Noble, Rene H. Gifford, Robert F. Labadie, Benoit M. Dawant
  • Patent number: 10508390
    Abstract: A method for making a plural-component, composite-material, highway dowel-bar including (1) preparing an elongate core train possessing endo-abutting, longitudinally alternating, (a) elongate, high-shear-strength, cylindrical cores having a common cross section, and (b) elongate, but shorter, cylindrical, fibre-reinforced plastic-resin end-plug blanks having opposite ends, and each having a cross section matching the cross section of the cores, (2) using the core train as a longitudinally moving mandrel, pultrusion-forming a fibre-reinforced plastic-resin sleeve continuously and bondedly around the core train so as to produce a pultrusion-result, intermediate, dowel-bar product, and (3) following pultrusion-forming, cross-cutting the intermediate, dowel-bar product at each longitudinal location therein which is intermediate the opposite ends of the end-plug blanks, thereby to form completed dowel bars.
    Type: Grant
    Filed: September 10, 2016
    Date of Patent: December 17, 2019
    Assignee: Composite Rebar Technologies, Inc.
    Inventors: Robert C. Gibson, Matthew H. Noble, Trent J. Garber
  • Patent number: 6373260
    Abstract: A single cable, single point stimulus and response probing system allows the measurement of both low impedance stimulus measurements and high impedance response measurements using a single probe cable. Circuitry located within the probe cable receives stimulus input from the stimulus circuitry located within a test and measurement device, and delivers input to response measurement circuitry also located within the test and measurement device. Certain embodiments of the probing system use feedback supplied to an amplifier located within the stimulus circuitry to improve the accuracy of the measurement device and control output impedance. Feedback can be locally supplied from the output of the stimulus circuitry, or can be generated using an additional amplifier located within the response measurement circuitry.
    Type: Grant
    Filed: February 24, 1998
    Date of Patent: April 16, 2002
    Assignee: Agilent Technologies, Inc.
    Inventors: Dennis J. Weller, Robert H. Noble
  • Patent number: 6059983
    Abstract: A method of fabricating an overcoated printed circuit board having a clean area free of contamination from the overcoating material. A metal-clad substrate is etched to form first and second printed circuit traces on the substrate. The first and second printed circuit traces define a channel having first and second ends. A layer of soldermask is deposited onto the substrate to cover a portion of the first and second printed circuit traces and to cover the channel except at an aperture. The aperture includes the intended clean area. The first and second printed circuit traces and the channel are covered with a capping device. An overcoating material is applied to the printed circuit board. During the applying step, the overcoating material is allowed to infiltrate into the channel under the capping device at the first and second ends, but is not allowed to reach the aperture.
    Type: Grant
    Filed: September 23, 1997
    Date of Patent: May 9, 2000
    Assignee: Hewlett-Packard Company
    Inventor: Robert H. Noble
  • Patent number: 5996100
    Abstract: A system and method for injecting and canceling a bias voltage in an attenuated circuit is presented. The attenuated circuit is disposed within a tri-state logic-level measurement apparatus. The bias voltage is provided to ensure that when the measurement apparatus is floating, it floats at the tri-state voltage. In one embodiment, a summing network is connected to an attenuator, a first voltage generator which provides a bias voltage and a second voltage generator which provides a cancellation voltage. In another embodiment, a FET amplifier is provided in place of the summing network.
    Type: Grant
    Filed: December 22, 1997
    Date of Patent: November 30, 1999
    Assignee: Hewlett-Packard Company
    Inventors: Robert H. Noble, Robert B. Smith
  • Patent number: 5977774
    Abstract: A method for determining whether a circuit under test is open is presented. A digital-to-analog converter is dithered to generate a known signal. This known signal is summed with an external attenuation signal which is brought into the system from a probe on the circuit under test. This summation is then measured by an analog-to-digital converter (ADC). If the known signal is not attenuated by the probe (i.e., the ADC measures essentially the known signal), we can conclude that the circuit is open.
    Type: Grant
    Filed: October 31, 1997
    Date of Patent: November 2, 1999
    Assignee: Hewlett-Packard Company
    Inventors: Robert H. Noble, Robert B. Smith
  • Patent number: 5969924
    Abstract: A printed circuit spark gap for an overcoated printed circuit board. A metal-clad substrate is etched to form first and second printed circuit traces on the substrate. The first and second printed circuit traces define a channel having first and second ends. A layer of soldermask is deposited onto the substrate to cover a portion of the first and second printed circuit traces and to cover the channel except at an aperture. The aperture includes the spark gap. The first and second printed circuit traces and the channel are covered with a capping device. An overcoating material is applied to the printed circuit board. During the applying step, the overcoating material is allowed to infiltrate into the channel under the capping device at the first and second ends, but is not allowed to reach the aperture. Counter pressure buildup inside the channel, caused by the infiltration itself, stops the overcoating material before it reaches the intended clean area.
    Type: Grant
    Filed: September 23, 1997
    Date of Patent: October 19, 1999
    Assignee: Hewlett Packard Company
    Inventor: Robert H. Noble
  • Patent number: 5942982
    Abstract: A system for detecting open circuits is presented. The system comprises first and second digital-to-analog converters (DACs). The DACs, in combination with a microprocessor, generate a tri-state voltage which is fed through the system. This tri-state voltage is then attenuated via an amplifier. A probe carries an external attenuation signal via a measurement line through the system to be summed with the attenuated tri-state voltage to create V.sub.wts. An analog-to-digital converter then compares V.sub.wts with a known signal to determine whether the circuit under test is open.
    Type: Grant
    Filed: October 31, 1997
    Date of Patent: August 24, 1999
    Assignee: Hewlett-Packard Company
    Inventors: Robert H. Noble, Robert B. Smith
  • Patent number: 5914870
    Abstract: A low power high efficiency power supply provides a high voltage level output, which can be used to drive a variety of devices. The power supply uses controlled feedback to a comparator, which in turn drives an AND gate logic device. The comparator drives the AND gate logic device to gate an input clock signal the output of the AND gate logic being supplied to a resonant circuit that is at or near the resonant frequency of the input clock signal. The output of the resonant circuit is rectified to provide the final voltage output. The final voltage output is attenuated and supplied as feedback to the comparator.
    Type: Grant
    Filed: December 18, 1997
    Date of Patent: June 22, 1999
    Assignee: Hewlett-Packard Company
    Inventors: Robert H. Noble, Robert B. Smith
  • Patent number: D399774
    Type: Grant
    Filed: October 31, 1997
    Date of Patent: October 20, 1998
    Assignee: Hewlett-Packard Company
    Inventor: Robert H. Noble