Abstract: A system for synchronizing a succession of horizontal deflection coil currents of a CRT display with a succession of synchronization signals includes a variable delay which is strobed by a synchronization signal and triggers the generation of a deflection current after a specified delay. The delay is automatically controlled by a feedback loop in which the present delay is measured by a set-reset flip-flop, the flip-flop providing an output pulse having a duration equal to the delay. An integrator averages a train of output pulses from the flip-flop, and combines a reference signal with the average value to provide the control signal for the delay. The system operates with minimal bandwidth and with dynamics which are free of acquisition constraints so as to provide minimal sensitity to noise.

Abstract: A color monitor having a highly accurate video processing circuit for providing a high accuracy color CRT display is disclosed which utilizes three feedback loops in each of the three primary color channels, each feedback loop including both the final video amplifier and the CRT in order to achieve equalization and stabilization of their combined signal-to-brightness transfer characteristics against both CRT and circuit drift. The video processor circuitry also includes a D/A converter for generating a signal representative of the desired amplitude component for each primary color from a three bit digital input. By utilizing the three feedback loops, the color produced in the CRT display is independent of the operator set brightness and contrast settings and is maintained to within 10% of its desired value over varying temperature and adverse environmental conditions.

Abstract: A color video monitor is disclosed which includes improved digital convergence using a plurality of memory means in which vertical convergence correction values are stored, one memory each for red, green, blue and lateral blue convergence values. Interpolation means provide additional values between the points stored in memory such that a smooth transition between successive lines of the display is achieved. The correction values stored in the memories are generated by means of a high-order polynomial function. The monitor employs synchronization circuitry which synchronizes all digital components to the supplied video signal including horizontal and vertical sync pulses and an external 36 MHz clock associated therewith.