Abstract: A method of manufacturing a semiconductor device with reduced shallow trench isolation defects and stress is disclosed. The disclosed method begins by providing a silicon substrate including a capping layer. A plurality of isolation trenches are then etched through the capping layer and into the silicon substrate to form a plurality of isolation regions in the silicon substrate. The isolation trenches are then filled with an oxide layer. The oxide layer and the capping layer are then polished back using techniques known in the art. After polishing, the semiconductor device is annealed between a temperature range of about 1150° C. to about 1200° C.

Abstract: A method for eliminating source/drain shorting generated during the highly-doped source/drain implant steps in a standard STI process is provided. This is achieved by reducing the RTA temperature to be less than 1000° C. so as to minimize enhanced doping diffusion. Further, the energy level for the highly-doped source/drain implant steps is increased so to compensate for poly depletion in the gate electrodes.

Abstract: A method of minimizing mechanical stress generated during the trench-forming/trench-filling process steps in a standard shallow trench isolation (STI) process is provided. This is achieved by forming trenches with a more sloped and smoother profile, and/or limiting the trench depth to be less than 0.4 &mgr;m, and/or reducing or increasing the trench densification temperature, and/or performing the densification step after the chemical-mechanical polishing step. In addition, a furnace TEOS oxide film is used as the trench-filling material.

Abstract: An improved process of programming and erasing an EEPROM memory cell in an array of identical cells uses a reduced voltage on the write transistor of the cell to be programmed or erased and at the same time applies smaller voltages across the relatively thin oxides of the write transistors of the other cells in the array so as to reduce oxide leakage and damage in those cells but without disturbing the information stored in those cells. The result is the ability to scale down the size of the EEPROM memory cell allowing enhanced economies and permitting faster program, erase and reading speeds.