Abstract: Multi-bank, dual-pipe SRAM systems, methods, processes of operating such SRAMs, and/or methods of fabricating multi-bank, dual-pipe SRAM are disclosed. For example, one illustrative multi-bank, dual-pipe SRAM may comprise features for capturing read and write addresses, splitting and/or combining them via one or more splitting/combining processes, and/or bussing them to the SRAM memory banks, where they may be read and written to a particular bank. Illustrative multi-bank, dual-pipe SRAMs and methods herein may also comprise features for capturing two beats of write data, splitting and/or combining them via one or more splitting/combining processes, and bussing them to each SRAM bank, where they may be split/combined/recombined via one or more processes to write data to particular memory bank(s).

Abstract: Embodiments are directed to managing user interactions with applications. If a user employs a client computer to interact with a testing environment test events may be provided to a measurement engine based on user interactions, such that, the test events may include device identifiers associated with the client computer. If the user interacts with the application on the client computer separate from the testing environment application events may be provided to the measurement engine based on user interactions with the application, such that, the application events include the device identifiers. The measurement engine may be employed to correlate the test events with the application events based on the device identifiers. Reports associated events and user interaction with the application may be provided.

Abstract: Systems and methods are disclosed for increasing the performance of static random access memory (SRAM). Various systems herein, for example, may include or involve dual- or multi-pipe, multi-bank SRAMs, such as Quad-B2 SRAMs. In one illustrative implementation, there is provided an SRAM memory device including a memory array comprising a plurality of SRAM banks and pairs of separate and distinct pipes associated with each of the SRAM banks, wherein each pair of pipes may provide independent access to its associated SRAM bank.

Abstract: Multi-bank SRAM devices, systems, methods of operating multi-bank SRAMs, and/or methods of fabricating multi-bank SRAM systems are disclosed. For example, illustrative multi-bank SRAMs and methods may include or involve features for capturing read and write addresses at a particular frequency, splitting and/or combining them via one or more splitting/combining processes, and bussing them to each SRAM bank, where they may be split and/or combined via one or more splitting/combining processes to read and write to a particular bank. Some implementations herein may also involve features for capturing two beats of write data at a particular frequency, splitting and/or combining them via one or more splitting/combining processes, and bussing them to each SRAM bank, where they may be split and/or combined via one or more splitting/combining processes for writing to a particular bank. Reading and writing to banks may occur at less than or equal to half the frequency of capture.

Abstract: Systems and methods are disclosed for increasing the performance of static random access memory (SRAM). Various systems herein, for example, may include or involve dual- or multi-pipe, multi-bank SRAMs, such as Quad-B2 SRAMs. In one illustrative implementation, there is provided an SRAM memory device including a memory array comprising a plurality of SRAM banks and pairs of separate and distinct pipes associated with each of the SRAM banks, wherein each pair of pipes may provide independent access to its associated SRAM bank.

Abstract: Multi-bank, dual-pipe SRAM systems, methods, processes of operating such SRAMs, and/or methods of fabricating multi-bank, dual-pipe SRAM are disclosed. For example, one illustrative multi-bank, dual-pipe SRAM may comprise features for capturing read and write addresses, splitting and/or combining them via one or more splitting/combining processes, and/or bussing them to the SRAM memory banks, where they may be read and written to a particular bank. Illustrative multi-bank, dual-pipe SRAMs and methods herein may also comprise features for capturing two beats of write data, splitting and/or combining them via one or more splitting/combining processes, and bussing them to each SRAM bank, where they may be split/combined/recombined via one or more processes to write data to particular memory bank(s).

Abstract: Multi-bank SRAM devices, systems, methods of operating multi-bank SRAMs, and/or methods of fabricating multi-bank SRAM systems are disclosed. For example, illustrative multi-bank SRAMs and methods may include or involve features for capturing read and write addresses at a particular frequency, splitting and/or combining them via one or more splitting/combining processes, and bussing them to each SRAM bank, where they may be split and/or combined via one or more splitting/combining processes to read and write to a particular bank. Some implementations herein may also involve features for capturing two beats of write data at a particular frequency, splitting and/or combining them via one or more splitting/combining processes, and bussing them to each SRAM bank, where they may be split and/or combined via one or more splitting/combining processes for writing to a particular bank. Reading and writing to banks may occur at less than or equal to half the frequency of capture.

Abstract: Systems and methods are disclosed for increasing the performance of static random access memory (SRAM). Various systems herein, for example, may include or involve dual- or multi-pipe, multi-bank SRAMs, such as Quad-B2 SRAMs. In one illustrative implementation, there is provided an SRAM memory device including a memory array comprising a plurality of SRAM banks and pairs of separate and distinct pipes associated with each of the SRAM banks, wherein each pair of pipes may provide independent access to its associated SRAM bank.

Abstract: Systems and methods are disclosed for increasing the performance of static random access memory (SRAM). Various systems herein, for example, may include or involve dual- or multi-pipe, multi-bank SRAMs, such as Quad-B2 SRAMs. In one illustrative implementation, there is provided an SRAM memory device including a memory array comprising a plurality of SRAM banks and pairs of separate and distinct pipes associated with each of the SRAM banks, wherein each pair of pipes may provide independent access to its associated SRAM bank.

Abstract: Systems and methods are disclosed for increasing the performance of static random access memory (SRAM). Various systems herein, for example, may include or involve dual- or multi-pipe, multi-bank SRAMs, such as Quad-B2 SRAMs. In one illustrative implementation, there is provided an SRAM memory device including a memory array comprising a plurality of SRAM banks and pairs of separate and distinct pipes associated with each of the SRAM banks, wherein each pair of pipes may provide independent access to its associated SRAM bank.

Abstract: Systems and methods are disclosed for increasing the performance of static random access memory (SRAM). Various systems herein, for example, may include or involve dual- or multi-pipe, multi-bank SRAMs, such as Quad-B2 SRAMs. In one illustrative implementation, there is provided an SRAM memory device including a memory array comprising a plurality of SRAM banks and pairs of separate and distinct pipes associated with each of the SRAM banks, wherein each pair of pipes may provide independent access to its associated SRAM bank.

Abstract: Controlling on-die termination on a bi-directional single-ended data bus carrying data between a controller and a memory device. The controller and the memory device respectively include input termination pull-ups and input termination pull-downs. An enabled state is maintained for the input termination pull-downs of the controller except when data is driven on the bi-directional single ended data bus by the controller. Similarly, an enabled state is maintained for the set of input termination pull-downs of the memory device except when data is driven on the bi-directional single ended data bus by the memory device. In conjunction with this, a disabled state is maintained for the input termination pull-ups of the memory device (or controller) except when data is being received from the bi-directional single-ended data bus by the memory device (or controller).

Abstract: Controlling on-die termination on a bi-directional single-ended data bus carrying data between a controller and a memory device. The controller and the memory device respectively include input termination pull-ups and input termination pull-downs. An enabled state is maintained for the input termination pull-downs of the controller except when data is driven on the bi-directional single ended data bus by the controller. Similarly, an enabled state is maintained for the set of input termination pull-downs of the memory device except when data is driven on the bi-directional single ended data bus by the memory device. In conjunction with this, a disabled state is maintained for the input termination pull-ups of the memory device (or controller) except when data is being received from the bi-directional single-ended data bus by the memory device (or controller).

Abstract: A dynamic I/O configuration and protocol includes a configurable data bus for optimizing data throughput. The configurable data bus includes multiple bi-directional data buses between a memory device and a controller to maximize the data transfer efficiency of operation sequences and thereby optimize data throughput to and from the memory device. Each of the bi-directional data buses are configured for utilization in both read operations from and write operations to the memory device. Using control input signal lines, the controller specifies a current operation to be performed and the data bus to be used to perform the current operation. The specific instructions that are provided from the controller to the memory device depend on the particular operation sequence being performed.

Abstract: A dynamic I/O configuration and protocol includes a configurable data bus for optimizing data throughput. The configurable data bus includes multiple bi-directional data buses between a memory device and a controller to maximize the data transfer efficiency of operation sequences and thereby optimize data throughput to and from the memory device. Each of the bi-directional data buses are configured for utilization in both read operations from and write operations to the memory device. Using control input signal lines, the controller specifies a current operation to be performed and the data bus to be used to perform the current operation. The specific instructions that are provided from the controller to the memory device depend on the particular operation sequence being performed.

Abstract: An oil reclamation process wherein oil containing liquid contaminants, principally water, in both a free and dissolved state is passed through a vessel maintained under vacuum where it passes over a dispersing material to increase its surface area and such exposure to vacuum within the vessel increases the vapor pressure of the water contained in the oil such that steam is generated through evaporation, the decontaminated oil and the steam generated then being separately removed from the vessel where the steam is then condensed and the water so produced is discharged to waste.