Abstract: A system and method for renewing the ability of a component to play digital content. A timer is established, and before the elapse of the timer the component is engaged with a battery charging cradle. By virtue of the component being engaged with the cradle, the timer is reset.

Abstract: A transmit digital processing system for wireless transmission of HDMI and/or DVI data using an FPGA. The FPGA converts the data into two data streams and includes a front end component multiplexing video data with control data. A complementary receive FPGA is also disclosed.

Abstract: A transmit digital processing system for wireless transmission of HDMI and/or DVI data using an FPGA. The FPGA converts the data into two data streams and includes a front end component multiplexing video data with control data. A complementary receive FPGA is also disclosed.

Abstract: The present embodiments provide apparatuses, systems and methods for that allow the booting of an embedded system from an off-board memory. In some embodiments, a system is provided that includes a circuit board comprising a processor, a memory, an operating system stored in the memory and utilized to at least in part control processor operation, and an external memory access comprising a first port onboard the circuit board, a local off-board memory, wherein the local off-board memory is coupled to the first port, and a root file system stored in the local off-board memory used while booting the operating system.

Abstract: A plurality of high-frequency beam-forming RF antenna arrays are used to enable parallel data transmission at multi-Gigabit per second data rates. In one embodiment, the 60 GHz band is used for parallel transmission of data from an antenna array printed on the substrate or packaging of an integrated circuit.

Abstract: Digital Visual Interface (DVI), or High Definition Multi-media Interface (HDMI), data is received from a source and sent to a transmitter chip that includes a transition minimized differential signaling (TMDS) receiver that outputs a 3-data and 1-clock physical signaling stream representing the DVI or HDMI data. This stream is rendered into I and Q data by an ASIC or FPGA and sent to a wireless transmitter for modulation, upconverting, and transmission to, e.g., a nearby display device without ever rendering the data into baseband video on the transmitter chip. The display device has a receiver chip that is essentially the inverse of the transmitter chip.

Abstract: In a wireless 60GHz data communication system, one or both of the source and receiver can have multiple antennae, with the antenna providing the best signal strength being dynamically selected. In this way, if a person or other object momentarily crosses between the source and receiver, blocking data communication from one antenna, the other antenna can be used.

Abstract: Methods and apparatus for optical wireless communication. In one embodiment, a wireless optical video system in which video content (e.g., DVI or HDMI) is transmitted wirelessly between a digital video source and a display device. This wireless optical communication is accomplished using a laser, encoded with the digital video data, directed from an optical transmitter to an optical receiver. In another embodiment, the data to be communicated includes high-definition video content.

Abstract: A transmit digital processing system for wireless transmission of HDMI and/or DVI data using an FPGA. The FPGA converts the data into two data streams and includes a front end component multiplexing video data with control data. A complementary receive FPGA is also disclosed.

Abstract: Digital Visual Interface (DVI), or High Definition Multi-media Interface (HDMI), data is received from a source and sent to a transmitter chip that includes a transition minimized differential signaling (TMDS) receiver that outputs a 3-data and 1-clock physical signaling stream representing the DVI or HDMI data. This stream is rendered into I and Q data by an ASIC or FPGA and sent to a wireless transmitter for modulation, upconverting, and transmission to, e.g., a nearby display device without ever rendering the data into baseband video on the transmitter chip. The display device has a receiver chip that is essentially the inverse of the transmitter chip.

Abstract: A system for sending multimedia data between a first High Definition Multimedia Interface (HDMI) component and a second HDMI component that is engaged with a displayer of multimedia data includes a first Digital Visual Interface (DVI) component receiving HDCP-encrypted multimedia data from the first HDMI component over a wire. A wireless transmitter sends data from the first DVI component to a wireless receiver, preferably at 60 GHz, and the receiver in turn sends the data to a second DVI component. Neither DVI component encrypts or decrypts data. The second DVI component sends the multimedia data to a second HDMI component for decryption and display on, e.g., an LCD or plasma display.

Abstract: Data such as high definition (HD) video may be sent from a transmitter such as a laptop computer to a receiver such as a video projector using a 60 GHz (and, hence, inherently directional, short range, and thus secure) forward channel wireless link. Encryption information such as encryption keys are also exchanged over the forward channel link. The encryption information is used to encrypt control signals that can be exchanged over a reverse channel link that may operate at a frequency of 2.4 GHz.

Abstract: Digital Visual Interface (DVI), or High Definition Multi-media Interface (HDMI), data is received from a source and sent to a transmitter chip that includes a transition minimized differential signaling (TMDS) receiver that outputs a 3-data and 1-clock physical signaling stream representing the DVI or HDMI data. This stream is rendered into I and Q data by an ASIC or FPGA and sent to a wireless transmitter for modulation, upconverting, and transmission to, e.g., a nearby display device without ever rendering the data into baseband video on the transmitter chip. The display device has a receiver chip that is essentially the inverse of the transmitter chip.

Abstract: A packetized voice telephony system including a set top box including a cable modem front end for supporting cable television services to be provided to a television coupled to the set top box. Also included is a voice peripheral coupled to the set top box for supporting packetized voice telephony services provided via a cable link and through the set top box. In one variation, the voice peripheral supports Voice over Internet Protocol (VoIP). The voice peripheral is external to the set top box and couples to the subscriber's telephone equipment. In some variations, the voice peripheral includes a power source to provide backup power to the set top box and the subscriber's telephone equipment.