Patents by Inventor Robert Haskell

Robert Haskell has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220358052
    Abstract: Each PIPT L2 cache entry is uniquely identified by a set index and a way and holds a generational identifier (GENID). The L2 detects a miss of a physical memory line address (PMLA). An L2 set index is obtained from the PMLA. The L2 picks a way for replacement, increments the GENID held in the entry in the picked way of the selected set, and forms a physical address proxy (PAP) for the PMLA with the obtained set index and the picked way. The PAP uniquely identifies the picked L2 entry. The L2 forms a generational PAP (GPAP) for the PMLA with the PAP and the incremented GENID. A load/store unit makes available the GPAP as a proxy of the PMLA for comparisons with GPAPs of other PMLAs, rather than making comparisons of the PMLA itself with the other PMLAs, to determine whether the PMLA matches the other PMLAs.
    Type: Application
    Filed: May 18, 2022
    Publication date: November 10, 2022
    Inventors: John G. Favor, Srivatsan Srinivasan, Robert Haskell Utley
  • Publication number: 20220358048
    Abstract: A cache memory subsystem includes virtually-indexed L1 and PIPT L2 set-associative caches having an inclusive allocation policy such that: when a first copy of a memory line specified by a physical memory line address (PMLA) is allocated into an L1 entry, a second copy of the line is also allocated into an L2 entry; when the second copy is evicted, the first copy is also evicted. For each value of the PMLA, the second copy can be allocated into only one L2 set, and an associated physical address proxy (PAP) for the PMLA includes a set index and way number that uniquely identifies the entry. For each value of the PMLA there exist two or more different L1 sets into which the first copy can be allocated, and when the L2 evicts the second copy, the L1 uses the PAP of the PMLA to evict the first copy.
    Type: Application
    Filed: May 24, 2022
    Publication date: November 10, 2022
    Inventors: John G. Favor, Srivatsan Srinivasan, Robert Haskell Utley
  • Publication number: 20220358046
    Abstract: A microprocessor includes a virtually-indexed L1 data cache that has an allocation policy that permits multiple synonyms to be co-resident. Each L2 entry is uniquely identified by a set index and a way number. A store unit, during a store instruction execution, receives a store physical address proxy (PAP) for a store physical memory line address (PMLA) from an L1 entry hit upon by a store virtual address, and writes the store PAP to a store queue entry. The store PAP comprises the set index and the way number of an L2 entry that holds a line specified by the store PMLA. The store unit, during the store commit, reads the store PAP from the store queue, looks up the store PAP in the L1 to detect synonyms, writes the store data to one or more of the detected synonyms, and evicts the non-written detected synonyms.
    Type: Application
    Filed: May 24, 2022
    Publication date: November 10, 2022
    Inventors: John G. Favor, Srivatsan Srinivasan, Robert Haskell Utley
  • Publication number: 20220358037
    Abstract: Each load/store queue entry holds a load/store physical address proxy (PAP) for use as a proxy for a load/store physical memory line address (PMLA). The load/store PAP comprises a set index and a way that uniquely identifies an L2 cache entry holding a memory line at the load/store PMLA when an L1 cache provides the load/store PAP during the load/store instruction execution. The microprocessor removes a line at a removal PMLA from an L2 entry, forms a removal PAP as a proxy for the removal PMLA that comprises a set index and a way, snoops the load/store queue with the removal PAP to determine whether the removal PAP is being used as a proxy for the removal PMLA, fills the removed entry with a line at a fill PMLA, and prevents the removal PAP from being used as a proxy for the removal PMLA and the fill PMLA concurrently.
    Type: Application
    Filed: May 18, 2022
    Publication date: November 10, 2022
    Inventors: John G. Favor, Srivatsan Srinivasan, Robert Haskell Utley
  • Publication number: 20220358039
    Abstract: A L2 cache is set associative, has N ways, and is inclusive of a virtual L1 cache such that when the virtual address misses in the L1: a portion of the virtual address is translated into a physical memory line address (PMLA), the PMLA is allocated into an L2 entry, and a physical address proxy (PAP) for the PMLA is allocated into an L1 entry. The PAP for the PMLA includes a set and a way that uniquely identify the L2 entry. The L2 receives a physical memory line address for allocation, uses a set index portion of the PMLA, and for each L2 way, forms a PAP corresponding to the way. The L1, for each PAP, generates a corresponding indicator of whether the PAP is L1 resident. The L2 selects, for replacement, a way whose indicator indicates the PAP is not resident in the L1.
    Type: Application
    Filed: May 24, 2022
    Publication date: November 10, 2022
    Inventors: John G. Favor, Srivatsan Srinivasan, Robert Haskell Utley
  • Patent number: 8102843
    Abstract: An apparatus and method are provided that enable I/O devices to be shared among multiple operating system domains. The apparatus has a first plurality of I/O ports, a second I/O port, and core logic. The first plurality of I/O ports is coupled to a plurality of operating system domains through a PCI Express fabric. Each of the first plurality of I/O ports is configured to route PCI Express transactions between said plurality of operating system domains and the switching apparatus. The second I/O port is coupled to a first shared input/output endpoint, where the first shared input/output endpoint is configured to request/complete said PCI Express transactions for each of the plurality of operating system domains. The core logic is coupled to the first plurality of I/O ports and the second I/O port. The core logic routes the PCI Express transactions between the first plurality of I/O ports and the second I/O port.
    Type: Grant
    Filed: April 19, 2004
    Date of Patent: January 24, 2012
    Assignee: Emulex Design and Manufacturing Corporation
    Inventors: Christopher J. Pettey, Asif Khan, Annette Pagan, Richard E. Pekkala, Robert Haskell Utley
  • Patent number: 7979592
    Abstract: A computer system includes a shared I/O device including functions providing access to device local memory space, and a plurality of roots coupled to the shared I/O device via a switch fabric. A first root assigns a first address in a first root memory space to a first function. A second root assigns a second address in a second root memory space to a second function. The switch fabric maps the first root memory space to a first portion of device local memory space and the second root memory space to a second portion of device local memory space. Subsequently, the switch receives a data transaction request from the first root targeted to the first address, translates the first address to a corresponding location in the first portion of the device local memory space based on the mapping, and routes the data transaction request to the I/O device.
    Type: Grant
    Filed: February 9, 2008
    Date of Patent: July 12, 2011
    Assignee: Emulex Design and Manufacturing Corporation
    Inventors: Christopher J. Pettey, Stephen Glaser, Asif Khan, Jon Nalley, Stephen Rousset, Tom Saeger, Robert Haskell Utley
  • Patent number: 7953074
    Abstract: An apparatus and method are provided that enable I/O devices to be shared among multiple operating system domains. The apparatus includes a first plurality of I/O ports, a second I/O port, and a plurality of port initialization logic elements. The first plurality of I/O ports is coupled to a plurality of operating system domains through a load-store fabric. Each of the first plurality of I/O ports routes transactions between the plurality of operating system domains and the switching apparatus. The second I/O port is coupled to a first shared input/output endpoint. The first shared input/output endpoint is configured to request/complete the transactions for each of the plurality of operating system domains. One of the plurality of port initialization logic elements is coupled to the second I/O port and remaining ones of the plurality of port initialization logic elements are each coupled to a corresponding one of the first plurality of I/O ports.
    Type: Grant
    Filed: January 31, 2005
    Date of Patent: May 31, 2011
    Assignee: Emulex Design and Manufacturing Corporation
    Inventors: Christopher J. Pettey, Asif Khan, Annette Pagan, Richard E. Pekkala, Robert Haskell Utley
  • Patent number: 7917658
    Abstract: An apparatus and method are provided that enable I/O devices to be shared among multiple operating system domains. The apparatus has a first plurality of I/O ports, a second I/O port, and link training logic. The first plurality of I/O ports is coupled to a plurality of operating system domains through a load-store fabric. Each of the first plurality of I/O ports is configured to route transactions between the plurality of operating system domains and the switching apparatus. The second I/O port is coupled to a first shared input/output endpoint. The first shared input/output endpoint is configured to request/complete the transactions for each of the plurality of operating system domains. The link training logic is coupled to the second I/O port. The link training logic initializes a link between the second I/O port and the first shared input/output endpoint to support the transactions corresponding to the each of the plurality of operating system domains.
    Type: Grant
    Filed: May 25, 2008
    Date of Patent: March 29, 2011
    Assignee: Emulex Design and Manufacturing Corporation
    Inventors: Christopher J. Pettey, Asif Khan, Annette Pagan, Richard E. Pekkala, Robert Haskell Utley
  • Publication number: 20110031289
    Abstract: A device for supporting an electronic device is disclosed and may include a wrist wrap. The wrist wrap may include an interior wrist wrap layer and an exterior wrist wrap layer. The device may also include at least one spring metal strip that may be disposed between the interior wrist wrap layer and the exterior wrist wrap layer. Further, the device may include at least one exterior fastener disposed on the exterior wrist wrap layer. The at least one exterior fastener may be configured to receive a fastener on a device engagement housing, a fastener on a portable electronic device, or a combination thereof.
    Type: Application
    Filed: August 10, 2009
    Publication date: February 10, 2011
    Inventors: Robert Haskell, John Eric Churilla, Hamid Veijl, Roy Paul Prosise, Curt Stewart
  • Patent number: 7836211
    Abstract: An apparatus and method are provided that enable I/O devices to be shared and/or partitioned among a plurality of operating system domains within the load-store fabric of each of the operating system domains without requiring modification to the operating system or driver software of the operating system domains. The apparatus includes sharing logic and a first shared input/output (I/O) endpoint. The sharing logic is coupled to a plurality of operating system domains through a load-store fabric. The sharing logic routes transactions between the plurality of operating system domains. The first shared input/output (I/O) endpoint is coupled to the sharing logic. The first shared I/O endpoint requests/completes the transactions for the each of said plurality of operating system domains according to a variant of a protocol that encapsulates an OS domain header within a transaction layer packet.
    Type: Grant
    Filed: March 16, 2004
    Date of Patent: November 16, 2010
    Assignee: Emulex Design and Manufacturing Corporation
    Inventors: Christopher J. Pettey, Asif Khan, Annette Pagan, Richard E. Pekkala, Robert Haskell Utley
  • Patent number: 7706372
    Abstract: An apparatus and method is provided for allowing I/O devices to be shared and/or partitioned among a plurality of processing complexes within the load/store fabric of each of the processing complexes without requiring modification to the operating system or driver software of the processing complexes. The apparatus and method includes a switch for selectively coupling each of the processing complexes to one or more shared I/O devices. The apparatus and method further includes placing information within packets transmitted between the switch and the I/O devices to identify which of the processing complexes the packets are associated with. The invention further includes an apparatus and method within the shared I/O devices to allow the shared I/O devices to service each of the processing complexes independently.
    Type: Grant
    Filed: April 19, 2006
    Date of Patent: April 27, 2010
    Assignee: NextIO Inc.
    Inventors: Christopher J. Pettey, Asif Khan, Annette Pagan, Richard E. Pekkala, Robert Haskell Utley
  • Patent number: 7698483
    Abstract: An apparatus has a first plurality of I/O ports, a second I/O port, and link training logic. The first plurality is coupled to a plurality of operating system domains through a load-store fabric. Each of the first plurality is configured to route transactions between the plurality of operating system domains and the switching apparatus. The second I/O port is coupled to a first shared input/output endpoint. The first shared input/output endpoint is configured to request/complete the transactions for each of the plurality of operating system domains. The link training logic is coupled to the second I/O port. The link training logic initializes a link between the second I/O port and the first shared input/output endpoint to support the transactions corresponding to the each of the plurality of operating system domains. The link is initialized in a manner that is transparent to the plurality of operating system domains.
    Type: Grant
    Filed: October 25, 2004
    Date of Patent: April 13, 2010
    Assignee: NextIO, Inc.
    Inventors: Christopher J. Pettey, Asif Khan, Annette Pagan, Richard E. Pekkala, Robert Haskell Utley
  • Patent number: 7620064
    Abstract: An apparatus and method is provided for allowing I/O devices to be shared and/or partitioned among a plurality of processing complexes within the load/store fabric of each of the processing complexes without requiring modification to the operating system or driver software of the processing complexes. The apparatus and method includes a switch for selectively coupling each of the processing complexes to one or more shared I/O devices. The apparatus and method further includes placing information within packets transmitted between the switch and the I/O devices to identify which of the processing complexes the packets are associated with. The invention further includes an apparatus and method within the shared I/O devices to allow the shared I/O devices to service each of the processing complexes independently.
    Type: Grant
    Filed: September 26, 2005
    Date of Patent: November 17, 2009
    Assignee: NextIO Inc.
    Inventors: Christopher J. Pettey, Asif Khan, Annette Pagan, Richard E. Pekkala, Robert Haskell Utley
  • Patent number: 7620066
    Abstract: An apparatus and method is provided for allowing I/O devices to be shared and/or partitioned among a plurality of processing complexes within the load/store fabric of each of the processing complexes without requiring modification to the operating system or driver software of the processing complexes. The apparatus and method includes a switch for selectively coupling each of the processing complexes to one or more shared I/O devices. The apparatus and method further includes placing information within packets transmitted between the switch and the I/O devices to identify which of the processing complexes the packets are associated with. The invention further includes an apparatus and method within the shared I/O devices to allow the shared I/O devices to service each of the processing complexes independently.
    Type: Grant
    Filed: September 26, 2005
    Date of Patent: November 17, 2009
    Assignee: NextIO Inc.
    Inventors: Christopher J. Pettey, Asif Khan, Annette Pagan, Richard E. Pekkala, Robert Haskell Utley
  • Patent number: 7457906
    Abstract: An apparatus and method is provided for allowing I/O devices to be shared and/or partitioned among a plurality of processing complexes within the load/store fabric of each of the processing complexes without requiring modification to the operating system or driver software of the processing complexes. The apparatus and method includes a switch for selectively coupling each of the processing complexes to one or more shared I/O devices. The apparatus and method further includes placing information within packets transmitted between the switch and the I/O devices to identify which of the processing complexes the packets are associated with. The invention further includes an apparatus and method within the shared I/O devices to allow the shared I/O devices to service each of the processing complexes independently.
    Type: Grant
    Filed: January 14, 2004
    Date of Patent: November 25, 2008
    Assignee: NextIO, Inc.
    Inventors: Christopher J. Pettey, Asif Khan, Annette Pagan, Richard E. Pekkala, Robert Haskell Utley
  • Publication number: 20080288664
    Abstract: An apparatus and method are provided that enable I/O devices to be shared among multiple operating system domains. The apparatus has a first plurality of I/O ports, a second I/O port, and link training logic. The first plurality of I/O ports is coupled to a plurality of operating system domains through a load-store fabric. Each of the first plurality of I/O ports is configured to route transactions between the plurality of operating system domains and the switching apparatus. The second I/O port is coupled to a first shared input/output endpoint. The first shared input/output endpoint is configured to request/complete the transactions for each of the plurality of operating system domains. The link training logic is coupled to the second I/O port. The link training logic initializes a link between the second I/O port and the first shared input/output endpoint to support the transactions corresponding to the each of the plurality of operating system domains.
    Type: Application
    Filed: May 25, 2008
    Publication date: November 20, 2008
    Applicant: NEXTIO INC.
    Inventors: Christopher J. Pettey, Asif Khan, Annette Pagan, Richard E. Pekkala, Robert Haskell Utley
  • Patent number: 7219183
    Abstract: An apparatus and method for sharing I/O devices. The apparatus has a first plurality of I/O ports, a second I/O port, and core logic. The first plurality is coupled to a plurality of operating system domains through a load-store fabric. Each of the first plurality routes transactions between the operating system domains and the switching apparatus. The second I/O port is coupled to a first shared input/output endpoint. The first shared input/output endpoint requests/completes transactions for each of the plurality of operating system domains. The core logic is coupled to the first plurality of I/O ports and the second I/O port. The core logic routes the transactions between the first plurality of I/O ports and the second I/O port and associates each of the transactions with a corresponding one of the plurality of operating system domains (OSDs) by encapsulating an OS domain header within a transaction layer packet.
    Type: Grant
    Filed: April 19, 2004
    Date of Patent: May 15, 2007
    Assignee: Nextio, Inc.
    Inventors: Christopher J. Pettey, Asif Khan, Annette Pagan, Richard E. Pekkala, Robert Haskell Utley
  • Patent number: 7188209
    Abstract: An apparatus having a first plurality of I/O ports, a second I/O port, and core logic. The first plurality of I/O ports is coupled to a plurality of operating system domains (OSDs) through a load-store fabric, each routing transactions between the plurality of OSDs and the switching apparatus. The second I/O port is coupled to a first shared input/output endpoint. The first shared input/output endpoint requests/completes the transactions for each of the plurality of OSDs. The core logic is coupled to the first plurality of I/O ports and the second I/O port. The core logic routes the transactions between the first plurality of I/O ports and the second I/O port. The core logic designates a corresponding one of the plurality of OSDs according to a variant of a protocol, where the protocol provides for routing of the transactions only for a single OSD.
    Type: Grant
    Filed: April 19, 2004
    Date of Patent: March 6, 2007
    Assignee: Nextio, Inc.
    Inventors: Christopher J. Pettey, Asif Khan, Annette Pagan, Richard E. Pekkala, Robert Haskell Utley
  • Patent number: 7174413
    Abstract: A method enabling I/O devices to be shared among multiple operating system domains, including first communicating with each of the operating system domains according to a protocol that provides exclusively for a single system domain ithin the load-store fabric; and second communicating with the shared I/O endpoint according to a variant of the protocol to enable the shared I/O endpoint to associate a prescribed operation with a corresponding one of the independent operating system domains. The second communicating includes encapsulating an OS domain header within a transaction layer packet that otherwise comports with the protocol, wherein the value of the OS domain header designates the corresponding one of the operating system domains; and via core logic within a swithching apparatus, mapping the independent operating system domains to the shared I/O endpoint.
    Type: Grant
    Filed: April 1, 2006
    Date of Patent: February 6, 2007
    Assignee: Nextio Inc.
    Inventors: Christopher J. Pettey, Asif Khan, Annette Pagan, Richard E. Pekkala, Robert Haskell Utley