Abstract: A structure is described having a plurality of electronic devices with the same or different internal CMOS voltages; an interconnection between two or more of the electronic devices; driver and receiver circuits which provide selectable input/output voltage levels for interfacing with several generations of CMOS technology, thus allowing chips fabricated in such technologies to communicate using a signal voltage range most suitable for each chip; Circuitry for selecting or adjusting the type of receiver circuit used, thus allowing either the use of a differential comparator circuit with an externally supplied reference voltage, or alternatively, the use of an inverter style receiver with an adjustable threshold, the selection being accomplished by setting the external reference to a predetermined voltage; Circuitry for selecting or adjusting the switching threshold of the inverter receiver circuit, which enables the threshold to be set appropriately for a given input signal voltage range.

Abstract: FDSOI devices and methods for the fabrication thereof are provided. In one aspect, a method for fabricating a device includes the following steps. A wafer is provided having a substrate, a BOX and a SOI layer. A hardmask layer is deposited over the SOI layer. A photoresist layer is deposited over the hardmask layer and patterned into groups of segments. A tilted implant is performed to damage all but those portions of the hardmask layer covered or shadowed by the segments. Portions of the hardmask layer damaged by the implant are removed. A first etch is performed through the hardmask layer to form a deep trench in the SOI layer, the BOX and at least a portion of the substrate. The hardmask layer is patterned using the patterned photoresist layer. A second etch is performed through the hardmask layer to form shallow trenches in the SOI layer.

Abstract: FDSOI devices and methods for the fabrication thereof are provided. In one aspect, a method for fabricating a device includes the following steps. A wafer is provided having a substrate, a BOX and a SOI layer. A hardmask layer is deposited over the SOI layer. A photoresist layer is deposited over the hardmask layer and patterned into groups of segments. A tilted implant is performed to damage all but those portions of the hardmask layer covered or shadowed by the segments. Portions of the hardmask layer damaged by the implant are removed. A first etch is performed through the hardmask layer to form a deep trench in the SOI layer, the BOX and at least a portion of the substrate. The hardmask layer is patterned using the patterned photoresist layer. A second etch is performed through the hardmask layer to form shallow trenches in the SOI layer.

Abstract: FDSOI devices and methods for the fabrication thereof are provided. In one aspect, a method for fabricating a device includes the following steps. A wafer is provided having a substrate, a BOX and a SOI layer. A hardmask layer is deposited over the SOI layer. A photoresist layer is deposited over the hardmask layer and patterned into groups of segments. A tilted implant is performed to damage all but those portions of the hardmask layer covered or shadowed by the segments. Portions of the hardmask layer damaged by the implant are removed. A first etch is performed through the hardmask layer to form a deep trench in the SOI layer, the BOX and at least a portion of the substrate. The hardmask layer is patterned using the patterned photoresist layer. A second etch is performed through the hardmask layer to form shallow trenches in the SOI layer.

Abstract: FDSOI devices and methods for the fabrication thereof are provided. In one aspect, a method for fabricating a device includes the following steps. A wafer is provided having a substrate, a BOX and a SOI layer. A hardmask layer is deposited over the SOI layer. A photoresist layer is deposited over the hardmask layer and patterned into groups of segments. A tilted implant is performed to damage all but those portions of the hardmask layer covered or shadowed by the segments. Portions of the hardmask layer damaged by the implant are removed. A first etch is performed through the hardmask layer to form a deep trench in the SOI layer, the BOX and at least a portion of the substrate. The hardmask layer is patterned using the patterned photoresist layer. A second etch is performed through the hardmask layer to form shallow trenches in the SOI layer.

Abstract: A sense amplifier for use in sensing a signal in an integrated circuit comprises an amplifier portion and an output portion. The amplifier portion comprises a gated diode having a gate terminal. The output portion comprises an output transistor in signal communication with the gate terminal of the gated diode and having a source terminal. A variable source voltage acts on the source terminal of the output transistor when the sense amplifier is in operation. The variable source voltage is temporarily altered when the sense amplifier is actively sensing the signal in the integrated circuit.

Abstract: A memory cell for use in an integrated circuit comprises a read transistor and a gated diode. The read transistor has a source terminal. The gated diode has a gate terminal in signal communication with the read transistor. A variable source voltage acts on the source terminal of the read transistor when the memory cell is in operation. The variable source voltage is temporarily altered when the memory cell is read. For example, the source voltage may be reduced when the read transistor is implemented using an N-type transistor and increased when the read transistor is implemented using P-type transistor. This acts to impart the memory cell with faster read speed, higher read margin, and lower standby current.

Abstract: An electronic apparatus is disclosed having: a plurality of electronic devices with the same or different internal voltages; an interconnection between two or more of the plurality of electronic devices; each of said two or more electronic devices has an internal voltage; driver and receiver circuits which send and receive signals at a selectable communication voltage levels for interfacing between said two or more electronic devices, at a common communication voltage which is less than the highest value of said internal voltages of said two or more electronic devices; a circuit for configuring the driver and receiver circuits; and the driver circuit are configured to have a substantially constant output impedance independent of their output voltage.

Abstract: An image sensor is described incorporating a plurality of detector cells arranged in an array where each detector cell has a MOSFET with a floating body and operable as a lateral bipolar transistor to amplify charge collected by the floating body. The invention overcomes the problem of insufficient charge being collected in detector cells formed on silicon-on-insulator (SOI) substrates due to silicon thickness and will also work in bulk silicon embodiments.

Abstract: Circuit and method aspects are provided for voltage level translation circuit for an output driver. In a circuit aspect, a circuit includes an input mechanism for receiving an internal data signal of a first predetermined voltage range, at least two stacked transistors coupled to the input mechanism, and a bias generator coupled to the input mechanism and the at least two stacked transistors, the bias generator ensuring that the at least two stacked transistors operate below a predetermined maximum device voltage. The circuit further includes an output mechanism coupled to the at least two stacked transistors, the output mechanism providing an external signal of a second predetermined voltage range.

Abstract: Circuit and method aspects for translating acceptable voltage levels from an external device to acceptable voltage levels of an internal device are provided. These aspects include coupling an input receiver between the external device and the internal device, the input receiver including a clamp device, and coupling a bias generator to the input receiver at the clamp device, wherein the bias generator ensures proper translation of a high level input signal from the external device by the input receiver. The bias generator further ensures that a predetermined maximum device voltage of the clamp device is not exceeded.

Abstract: A FET band-gap reference generating circuit having a two-branch differential amplifier with a saturation state FETs for equal branch current, independent of power supply voltage, with a feedback connection to a reference FET in one branch, for driving the steady state output to the threshold voltage of the reference FET, also independent of the power supply voltage. A multistage circuit connects a divided down output of a first FET band-gap reference generating circuit to a current bias terminal of similar second FET based differential amplifier so that the steady state output of the second amplifier is equal to the sum of the divided down output and a threshold voltage of a second reference FET in the second amplifier.

Abstract: A fabrication method for providing electrical isolation between transistors such as field effect transistors (FETs) which are fabricated on the same semiconductive substrate is described that uses a single doping step to form both the channel stopper field doping and the FET channel doping. An example of an n-channel FET embodiment is described wherein an extra p-type doping is provided in the field region which serves to prevent parasitic conductive channels from occurring under the thick field oxide. Such parasitic channels can undesirably cause electrical shorting between adjacent FETs of an integrated circuit. Extra p-type doping is also provided in the FET channel region and serves to raise the gate threshold voltage of the enhancement-mode FET to a level suitable for integrated circuit operation. In the described method a single implantation or diffusion doping step provides both the field and channel doping regions, thereby reducing the number of processing steps.

Abstract: A method of fabricating a field effect transistor (FET) wherein a self-registered or misregistration tolerant electrical connection is provided between the gate electrode and a metallic interconnection line. The method involves a unique structure which includes a thick deposited oxide insulation layer and an etch stopping layer over doped silicon source and drain regions, over polysilicon gate electrode regions, and over field isolation regions. The etch stopping layer facilitates fabrication of a self-registering electrical connection between the gate electrode and a metallic interconnection line wherever desired. The thick deposited oxide layer provides reduced capacitive coupling between the insulated regions and the metallic interconnection line when compared to known self-registered gate contacting methods that employ only thermally grown oxide insulation.