Abstract: A semiconductor power device includes a drift region of a first conductivity type, a well region extending above the drift region and having a second conductivity type opposite the first conductivity type, an active trench extending through the well region and into the drift region, source regions having the first conductivity type formed in the well region adjacent the active trench, and a first termination trench extending below the well region and disposed at an outer edge of an active region of the device. The sidewalls and bottom of the active trench are lined with dielectric material, and substantially filled with a first conductive layer forming an upper electrode and a second conductive layer forming a lower electrode, the upper electrode being disposed above the lower electrode and separated therefrom by inter-electrode dielectric material.

Abstract: A method for forming thick oxide at the bottom of a trench formed in a semiconductor substrate includes forming a conformal oxide film that fills the trench and covers a top surface of the substrate. and etching the oxide film off the top surface of the substrate and inside the trench to leave a substantially flat layer of oxide having a target thickness at the bottom of the trench. The oxide film can be deposited by sub-atmospheric chemical vapor deposition processes, directional Tetraethoxysilate (TEOS) processes, or high density plasma deposition processes that form a thicker oxide at the bottom of the trench than on the sidewalls of the trench.

Abstract: A field effect transistor (FET) includes a trench extending into a silicon region of a first conductive type. A shield insulated from the silicon region by a shield dielectric extends in a lower portion of the trench. A gate electrode is in the trench over but insulated from the shield electrode by an inter-poly dielectric (IPD). The IPD comprises a conformal layer of dielectric and a thermal oxide layer.

Abstract: A method of forming shielded gate trench FET includes the following steps. A trench is formed in a silicon region of a first conductivity type. A shield electrode is formed in a bottom portion of the trench. An inter-poly dielectric (IPD) including a layer of thermal oxide and a layer of conformal dielectric is formed along an upper surface of the shield electrode. A gate dielectric lining at least upper trench sidewalls is formed. A gate electrode is formed in the trench such that the gate electrode is insulated from the shield electrode by the IPD.

Abstract: A semiconductor device is formed as follows. A plurality of trenches is formed in a silicon layer. An insulating layer filling an upper portion of each trench is formed. Exposed silicon is removed from adjacent the trenches to expose an edge of the insulating layer in each trench, such that the exposed edge of the insulating layer in each trench defines a portion of each contact opening formed between every two adjacent trenches.

Abstract: An implant capable of forming a differential image in an eye is shown. The implant comprises an elongated member having a pair of spaced ends. The elongated member is formed of a dimension to be inserted into and/or passed through a punctum opening of an eye and into the canaliculus. The implant comprises an energy obstructing material, such as for example a pigment comprising titanium dioxide, which is responsive to the application of an energy wave in the visible light range which, upon everting of an eyelid of an eye and exposing the implant to the energy wave, forms a differential image pattern showing the location of the implant in the canaliculus of the eye.

Abstract: An implant capable of forming a differential image in an eye is shown. The implant comprises an elongated member having a pair of spaced ends wherein one of the pair of ends includes a distal section that extends in a direction substantially parallel to the central axis. The elongated member and the distal section are formed of a dimension to be inserted into and/or passed through a punctum opening of an eye and into the canaliculus. The implant incorporates into at least one of the elongated member and the distal section an energy obstructing material responsive to the application of an energy wave, such as an energy wave in the form of sound waves vibrating at frequencies greater than 20,000 cycles per second or electromagnetic radiation, which upon everting of an eyelid of an eye and exposing the implant to an appropriate energy wave, forms a differential image pattern showing the location of the implant in the eye.

Abstract: A shielded gate trench FET is formed as follows. A trench is formed in a silicon region of a first conductivity type, the trench including a shield electrode insulated from the silicon region by a shield dielectric. An inter-poly dielectric (IPD) including a layer of thermal oxide and a layer of conformal dielectric is formed along an upper surface of the shield electrode. A gate dielectric lining at least upper trench sidewalls is formed. A gate electrode is formed in the trench such that the gate electrode is insulated from the shield electrode by the IPD.

Abstract: Various embodiments for improved power devices as well as their methods of manufacture, packaging and circuitry incorporating the same for use in a wide variety of power electronic applications are disclosed. One aspect of the invention combines a number of charge balancing techniques and other techniques for reducing parasitic capacitance to arrive at different embodiments for power devices with improved voltage performance, higher switching speed, and lower on-resistance. Another aspect of the invention provides improved termination structures for low, medium and high voltage devices. Improved methods of fabrication for power devices are provided according to other aspects of the invention. Improvements to specific processing steps, such as formation of trenches, formation of dielectric layers inside trenches, formation of mesa structures and processes for reducing substrate thickness, among others, are presented.

Abstract: Various embodiments for improved power devices as well as their methods of manufacture, packaging and circuitry incorporating the same for use in a wide variety of power electronic applications are disclosed. One aspect of the invention combines a number of charge balancing techniques and other techniques for reducing parasitic capacitance to arrive at different embodiments for power devices with improved voltage performance, higher switching speed, and lower on-resistance. Another aspect of the invention provides improved termination structures for low, medium and high voltage devices. Improved methods of fabrication for power devices are provided according to other aspects of the invention. Improvements to specific processing steps, such as formation of trenches, formation of dielectric layers inside trenches, formation of mesa structures and processes for reducing substrate thickness, among others, are presented.

Abstract: Self-aligned trench MOSFETs and methods for manufacturing the same are disclosed. By having a self-aligned structure, the number of MOSFETS per unit area—the cell density—is increased, making the MOSFETs cheaper to produce. The self-aligned structure for the MOSFET is provided by making the sidewall of the overlying isolation dielectric layer substantially aligned with the sidewall of the gate conductor. Such an alignment can be made through any number of methods such as using a dual dielectric process, using a selective dielectric oxidation process, using a selective dielectric deposition process, or a spin-on-glass dielectric process.

Abstract: A semiconductor device is formed as follows. A plurality of trenches is formed in a silicon layer. An insulating layer filling an upper portion of each trench is formed. Exposed silicon is removed from adjacent the trenches to expose an edge of the insulating layer in each trench, such that the exposed edge of the insulating layer in each trench defines a portion of each contact opening formed between every two adjacent trenches.

Abstract: A method for detecting a passivation pinhole includes forming an oxide vertical cavity surface-emitting laser (VCSEL) having an oxidation cavity, forming a passivation layer over a surface of the oxidation cavity, exposing the oxide VCSEL to an etchant vapor, and inspecting the oxide VCSEL for a defect caused by the etchant vapor.

Abstract: Various embodiments for improved power devices as well as their methods of manufacture, packaging and circuitry incorporating the same for use in a wide variety of power electronic applications are disclosed. One aspect of the invention combines a number of charge balancing techniques and other techniques for reducing parasitic capacitance to arrive at different embodiments for power devices with improved voltage performance, higher switching speed, and lower on-resistance. Another aspect of the invention provides improved termination structures for low, medium and high voltage devices. Improved methods of fabrication for power devices are provided according to other aspects of the invention. Improvements to specific processing steps, such as formation of trenches, formation of dielectric layers inside trenches, formation of mesa structures and processes for reducing substrate thickness, among others, are presented.

Abstract: In accordance with an embodiment of the present invention, a semiconductor device is formed as follows. An exposed surface area of a silicon layer where silicon can be removed is defined. A portion of the silicon layer is removed to form a middle section of a trench extending into the silicon layer from the exposed surface area of the silicon layer. Additional exposed surface areas of the silicon layer where silicon can be removed are defined. Additional portions of the silicon layer are removed to form outer sections of the trench such that the outer sections of the trench extend into the silicon layer from the additional exposed surface areas of the silicon layer. The middle section of the trench extends deeper into the silicon layer than the outer sections of the trench.

Abstract: In accordance with an embodiment of the present invention, a semiconductor device is formed as follows. An exposed surface area of a silicon layer where silicon can be removed is defined. A portion of the silicon layer is removed to form a middle section of a trench extending into the silicon layer from the exposed surface area of the silicon layer. Additional exposed surface areas of the silicon layer where silicon can be removed are defined. Additional portions of the silicon layer are removed to form outer sections of the trench such that the outer sections of the trench extend into the silicon layer from the additional exposed surface areas of the silicon layer. The middle section of the trench extends deeper into the silicon layer than the outer sections of the trench.

Abstract: A method and apparatus are provided for separating a discrete element from a first substrate web, moving at a first speed, and placing the discrete element on a second substrate web, moving at a second speed. The apparatus includes a first station, wherein perforations are made in the first substrate web, and a second station, wherein the discrete element is separated from the first substrate web at a line of perforations and the discrete element is transferred to a positioned on the second substrate web. The first station includes a perforation cutter assembly and conveyer assembly. The perforation cutter assembly includes first and second rollers with a cutting blade, with a discontinuous edge, and an anvil surface, respectively, to make perforations in the first substrate web. The second station includes a separation and transfer mechanism having separation and transfer segments for separating and transferring the discrete element from the first substrate web to the second substrate web.

Abstract: Self-aligned trench MOSFETs and methods for manufacturing the same are disclosed. By having a self-aligned structure, the number of MOSFETS per unit area—the cell density—is increased, making the MOSFETs cheaper to produce. The self-aligned structure for the MOSFET is provided by making the sidewall of the overlying isolation dielectric layer substantially aligned with the sidewall of the gate conductor. Such an alignment can be made through any number of methods such as using a dual dielectric process, using a selective dielectric oxidation process, using a selective dielectric deposition process, or a spin-on-glass dielectric process.

Abstract: A method and apparatus are provided for separating a discrete element from a first substrate web, moving at a first speed, and placing the discrete element on a second substrate web, moving at a second speed. The apparatus includes a first station, wherein perforations are made in the first substrate web, and a second station, wherein the discrete element is separated from the first substrate web at a line of perforations and the discrete element is transferred to a positioned on the second substrate web. The first station includes a perforation cutter assembly and conveyer assembly. The perforation cutter assembly includes first and second rollers with a cutting blade, with a discontinuous edge, and an anvil surface, respectively, to make perforations in the first substrate web. The second station includes a separation and transfer mechanism having separation and transfer segments for separating and transferring the discrete element from the first substrate web to the second substrate web.

Abstract: A method and apparatus are provided for separating a discrete element from a first substrate web, moving at a first speed, and placing the discrete element on a second substrate web, moving at a second speed. The apparatus includes a first station, wherein perforations are made in the first substrate web, and a second station, wherein the discrete element is separated from the first substrate web at a line of perforations and the discrete element is transferred to a positioned on the second substrate web. The first station includes a perforation cutter assembly and conveyer assembly. The perforation cutter assembly includes first and second rollers with a cutting blade, with a discontinuous edge, and an anvil surface, respectively, to make perforations in the first substrate web. The second station includes a separation and transfer mechanism having separation and transfer segments for separating and transferring the discrete element from the first substrate web to the second substrate web.