Patents by Inventor Robert Hillard

Robert Hillard has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200046478
    Abstract: The mouthpiece includes an arch-shaped guard having an inner surface. The inner surface is contoured to follow a shape of a dentition. The arch-shaped guard is sized to span at least a portion of upper teeth and a portion of lower teeth in the dentition. The mouthpiece includes a bite plate positioned along the inner surface and dividing the arch-shaped guard into an upper and lower portion. The mouthpiece includes a first light array arranged along the lower portion of the arch-shaped guard, and a second light array arranged along the upper portion of the arch-shaped guard. The first and second light arrays are arranged at offset distances from the bite plate where the offset distance of the second light array is greater than the offset distance of the first light array. The first and second light arrays are arranged to direct light onto the upper and lower teeth, respectively.
    Type: Application
    Filed: August 10, 2018
    Publication date: February 13, 2020
    Inventors: Russ Stewart, Robert Hillard, Jan Lombardo
  • Patent number: 8584843
    Abstract: At least one embodiment of a package system for particulate organic product includes a box element and an insert element. The box element generally includes a side pocket for retaining an auxiliary packet, such as a packet of cigarette rolling papers. The insert element acts as a transparent window aligned with one or more window apertures in the first face panel of the box element, and is extendable from the box element to provide a tray which can be partitioned into a product measurement zone and a product retentions zone. The partitioning may be provided by a foldable closure panel and associated tuck flap acting in cooperation with one another. The box element and insert element may be formed from respective pre-cut and scored blanks.
    Type: Grant
    Filed: March 6, 2012
    Date of Patent: November 19, 2013
    Inventor: Robert Hillard
  • Publication number: 20130233743
    Abstract: At least one embodiment of a package system for particulate organic product includes a box element and an insert element. The box element generally includes a side pocket for retaining an auxiliary packet, such as a packet of cigarette rolling papers. The insert element acts as a transparent window aligned with one or more window apertures in the first face panel of the box element, and is extendable from the box element to provide a tray which can be partitioned into a product measurement zone and a product retentions zone. The partitioning may be provided by a foldable closure panel and associated tuck flap acting in cooperation with one another. The box element and insert element may be formed from respective pre-cut and scored blanks.
    Type: Application
    Filed: March 6, 2012
    Publication date: September 12, 2013
    Inventor: Robert Hillard
  • Publication number: 20120042883
    Abstract: A composite packaging system for particulate smokable product comprises an aggregate of particulate smokable product, a bag element of organic polymeric film, an envelope element of metallized organic polymeric film, and at least one externally viewable image disposed on the envelope element. The bag element includes a distribution zone within which the aggregate is generally evenly distributed along an elongated profile. The bag element is rolled about its distribution zone, and along with the aggregate, is snugly retained within a hermetically sealed cavity of the envelope element. What results is a packaging system which is compact, lightweight, attractive and low-cost, yet capable of maintaining the freshness and flocculence of the smokable product throughout shipment, retail display and consumer handling of the packaged product.
    Type: Application
    Filed: August 17, 2010
    Publication date: February 23, 2012
    Applicant: Internationl Oddities, Inc.
    Inventor: Robert Hillard
  • Publication number: 20070109007
    Abstract: A semiconductor wafer or sample having a substrate of semiconducting material is tested by compressing a dielectric between three electrically conductive contacts and a top surface of the semiconductor wafer or sample substrate. The dielectric has a thickness that permits tunneling current to flow therethrough without damaging the dielectric. A first electrical bias is applied to a pair of adjacent contacts and a second electrical bias, such as ground reference, is applied to the other contact whereupon an inversion layer forms in the semiconductor wafer or sample. A value of a current that flows in the semiconductor wafer or sample substrate and across the dielectric, in the form of a tunneling current, is measured in response to the applied electrical biases. A surface mobility of minority carriers in the semiconductor wafer or sample is determined as a function of the applied electrical biases and the value of the measured current.
    Type: Application
    Filed: November 17, 2005
    Publication date: May 17, 2007
    Applicant: Solid State Measurements, Inc.
    Inventor: Robert Hillard
  • Publication number: 20070046310
    Abstract: In a method and apparatus for determining one or more electrical properties of a semiconductor wafer or sample, the response of a semiconductor wafer or sample to an applied CV-type electrical stimulus is measured. Utilizing a recursive technique, progressively more accurate values of equivalent oxide thickness CET, maximum capacitance Cox, flatband voltage Vfb and other properties of the semiconductor wafer or sample are determined from the measured response. An equivalent oxide thickness EOT of the semiconductor wafer or sample can be determined as a function of the most accurate value of CET determined based upon convergence of at least one of (1) the last two values of Cox or (2) the last two values of Vfb within a predetermined convergence criteria. One or more of the EOT value and/or values of one or more of CET, Cox or Vfb can then be output in a human detectable form.
    Type: Application
    Filed: August 31, 2005
    Publication date: March 1, 2007
    Applicant: Solid State Measurements, Inc.
    Inventors: Robert Hillard, Louison Tan
  • Publication number: 20050287684
    Abstract: To detect soft breakdown of a dielectric layer of a semiconductor wafer, a DC current is caused to flow between a top surface of the dielectric layer and the semiconducting material of the semiconductor wafer. The DC current is either a constant value DC current, or a DC current that swept and/or stepped from a first value toward a second value in a manner whereupon the electric field and, hence, a DC voltage induced across the dielectric layer increases as the DC current approaches the second value. The response of the semiconductor wafer to the flow of DC current is measured for the presence of an AC voltage component superimposed on the DC voltage. The value of the DC voltage induced across the dielectric layer where the AC voltage component is detected is designated as the soft breakdown voltage of the dielectric layer.
    Type: Application
    Filed: June 28, 2004
    Publication date: December 29, 2005
    Applicant: Solid State Measurements, Inc.
    Inventors: William Howland, Robert Hillard
  • Publication number: 20050287683
    Abstract: To determine the generation lifetime of a pn junction of a semiconductor wafer, an elastically deformable, electrically conductive contact is caused to touch a surface of the semiconductor wafer over the pn junction. At least one reverse bias voltage is applied to the pn junction via the contact and a value of current flowing in the contact in response to the application of each reverse bias voltage is measured. The generation lifetime of the pn junction is then determined from a subset of the values of the reverse bias voltage and the corresponding values of measured current.
    Type: Application
    Filed: June 23, 2004
    Publication date: December 29, 2005
    Applicant: Solid State Measurements, Inc.
    Inventor: Robert Hillard
  • Publication number: 20050253618
    Abstract: In a method of measuring at least one electrical property of a semiconductor wafer, an elastically deformable conductive contact formed from an electrically conductive coating overlaying an electrically conductive base material is provided. The base material has a first work function and the coating has a second work function. A first electrical contact is formed between the conductive contact and a top surface of a semiconductor wafer. A second electrical contact is formed with the semiconductor wafer. An electrical stimulus is applied between the first and second electrical contacts and a response of the semiconductor wafer to the electrical stimulus is measured. At least one electrical property of the semiconductor wafer is determined from the response.
    Type: Application
    Filed: May 14, 2004
    Publication date: November 17, 2005
    Applicants: Solid State Measurements, Inc., Applied Materials, Inc.
    Inventors: William Howland, Robert Hillard, Steven Hung
  • Publication number: 20050225345
    Abstract: A sheet resistance test of a wafer or sample can be performed by causing a plurality of spaced contacts, each of which either does not form oxides thereon or which forms conductive oxides thereon, to touch a surface of the wafer without penetrating or damaging the surface. An electrical stimulus is then applied to the wafer via one or more of the contacts and the electrical response of the semiconducting material to the electrical stimulus is detected via one or more of the contacts. At least one electrical property of the wafer can be determined from the measured response and the applied electrical stimulus.
    Type: Application
    Filed: April 5, 2005
    Publication date: October 13, 2005
    Applicant: Solid State Measurements, Inc.
    Inventors: Robert Mazur, Robert Hillard, James Healy
  • Publication number: 20050095728
    Abstract: A method of characterizing a silicon-on-insulator (SOI) wafer, comprised of an insulating layer sandwiched between a semiconductor top layer and a semiconductor substrate, includes moving a pair of spaced conductors into contact with a surface of the wafer exposed on a side thereof opposite the substrate. First and second biases are applied to the substrate and at least one of the conductors. At least one of the first and second biases are swept from a first value toward a second value and the current flowing through the SOI wafer in response to said sweep is measured. At least one characteristic of the wafer is determined from the measured current as a function of the one swept bias.
    Type: Application
    Filed: November 5, 2003
    Publication date: May 5, 2005
    Inventor: Robert Hillard
  • Publication number: 20050093563
    Abstract: A leakage current of a dielectric overlaying a semiconductor wafer can be determined by moving a conductive probe into contact with the dielectric and applying an electrical stimulus, in the form of a fixed amplitude, fixed frequency AC voltage superimposed on a DC voltage which is swept from a starting voltage towards an ending voltage, between the probe tip and the semiconductor wafer. Conductance values associated with the dielectric and the semiconductor wafer can be determined from phase angles between the AC voltage and an AC current resulting from the applied AC voltage during the sweep of the DC voltage. The leakage current of the dielectric can then be determined from the thus determined conductance values.
    Type: Application
    Filed: November 4, 2003
    Publication date: May 5, 2005
    Inventor: Robert Hillard