Patents by Inventor Robert Horn

Robert Horn has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250342955
    Abstract: The present disclosure relates to a call light monitoring system designed to enhance response efficiency and patient care management in healthcare facilities. This system includes unobtrusive monitoring capabilities that detect the activation of call lights without interfering with existing facility infrastructure. The system features a real-time display that provides immediate visual feedback on the duration of active call lights, enabling staff to prioritize responses based on urgency and elapsed time. Additionally, the system includes a comprehensive reporting module that records and analyzes the history of call light durations. This historical data can be used for performance evaluations, optimizing staff allocations, and identifying patterns that may indicate areas needing process improvement. The integration of these features into a single system provides a robust tool for improving patient satisfaction and operational efficiency in healthcare settings.
    Type: Application
    Filed: May 2, 2024
    Publication date: November 6, 2025
    Inventors: Michael Forsgren, Robert Horn
  • Patent number: 11733878
    Abstract: A Data Storage Device (DSD) includes one or more magnetic disks. One or more data blocks are encoded into a first plurality of Error Correction Code (ECC) sub-blocks including a first ECC sub-block. The first plurality of ECC sub-blocks is encoded into a first ECC super-block. The first ECC sub-block is write-verified by reading the first ECC super-block. If the write-verify passes, a second plurality of ECC sub-blocks is encoded into a subsequent ECC super-block. If the write-verify fails, the first ECC sub-block and a subset of the second plurality of ECC sub-blocks are encoded into the subsequent ECC super-block. In another aspect, in response to the first ECC super-block failing to recover the first ECC sub-block, a subsequent ECC super-block is read and a copy of the first ECC sub-block is used if the copy is detected in the subsequent ECC super-block.
    Type: Grant
    Filed: March 29, 2022
    Date of Patent: August 22, 2023
    Assignee: Western Digital Technologies, Inc.
    Inventors: Robert Horn, Derrick Burton
  • Patent number: 11657848
    Abstract: A Data Storage Device (DSD) includes one or more magnetic disks with each magnetic disk including at least one recording surface. A segment mapping is generated having a predetermined number of segment entries per recording surface with each segment entry corresponding to a data segment of the recording surface. One or more segment entries include a first logical address corresponding to a first logical data block that begins in the corresponding data segment and at least one of the data segments is configured to store multiple logical data blocks. A target segment entry is located in the segment mapping corresponding to a highest logical address less than or equal to a requested logical address of a read command and a head of the DSD is moved to a beginning portion of a target data segment corresponding to the target segment entry to perform the read command.
    Type: Grant
    Filed: February 24, 2022
    Date of Patent: May 23, 2023
    Assignee: Western Digital Technologies, Inc.
    Inventor: Robert Horn
  • Patent number: 11074129
    Abstract: Example storage systems, storage nodes, and methods provide erasure coding of data shards containing multiple data objects. Storage nodes store data shards having a data shard size and each containing a plurality of data objects, where the sum of the data object sizes is less than the data shard size. Some storage nodes store a parity shard containing parity data for the other data shards.
    Type: Grant
    Filed: October 31, 2019
    Date of Patent: July 27, 2021
    Assignee: Western Digital Technologies, Inc.
    Inventor: Robert Horn
  • Publication number: 20210133026
    Abstract: Example storage systems, storage nodes, and methods provide erasure coding of data shards containing multiple data objects. Storage nodes store data shards having a data shard size and each containing a plurality of data objects, where the sum of the data object sizes is less than the data shard size. Some storage nodes store a parity shard containing parity data for the other data shards.
    Type: Application
    Filed: October 31, 2019
    Publication date: May 6, 2021
    Inventor: Robert Horn
  • Patent number: 7404021
    Abstract: An integrated I/O controller in an integrated circuit is provided for centralized data management. The integrated circuit includes a host interface, a disk interface, and a mapping controller implemented in hardware to speed data processing and provide fault tolerance as exemplified with RAID configurations. The mapping controller provides block mapping across a plurality of peripherals or disk drives in a disk array. The integrated I/O controller can be utilized in storage area network systems and network area storage systems as well as other networking systems or devices.
    Type: Grant
    Filed: August 6, 2004
    Date of Patent: July 22, 2008
    Assignee: Aristos Logic Corporation
    Inventors: Virgil Wilkins, Robert Horn, Marc Acosta, Sanjay Mathur
  • Patent number: 7139931
    Abstract: A method of volume rebuilding in a RAID for a networked storage system in which portions of a hard disk drive under rebuild are progressively made available to the system during the rebuild process as the portions are rebuilt. The impact of rebuild activity on system performance is controllable by allowing non-rebuild requests to throttle rebuild requests.
    Type: Grant
    Filed: November 18, 2002
    Date of Patent: November 21, 2006
    Assignee: Aristos Logic Corporation
    Inventor: Robert Horn
  • Patent number: 7043610
    Abstract: A disk array includes a system and method for cache management and conflict detection. Incoming host commands are processed by a storage controller, which identifies a set of at least one cache segment descriptor (CSD) associated with the requested address range. Command conflict detection can be quickly performed by examining the state information of each CSD associated with the command. The use of CSDs therefore permits the present invention to rapidly and efficiently perform read and write commands and detect conflicts.
    Type: Grant
    Filed: May 5, 2003
    Date of Patent: May 9, 2006
    Assignee: Aristos Logic Corporation
    Inventors: Robert Horn, Biswajit Khandai
  • Publication number: 20050172504
    Abstract: A digital display compass for mounting on vehicle rear view mirrors, including a direction sensor module generating signals corresponding to a direction that it is facing attached to the inside of the vehicle windshield, an electronic housing attached to the back side of the rear view mirror, and a digital display attached to the front side of the rear view mirror. A flexible transmission cord extends from the directional sensor module to the electronic housing, and transmits the signals from the direction sensor module. The electronic housing contains a battery power source and electronics for converting the signals received from the transmission cord to drive a digital display representative of the direction sensed by the direction sensor module. A flexible cable extends from the back side of the mirror to the front side of the mirror and provides electronic communication from the electronic housing to the digital display.
    Type: Application
    Filed: February 9, 2004
    Publication date: August 11, 2005
    Inventors: Patrick Ohm, Robert Horn, Hong-Chung Chang
  • Patent number: 6912643
    Abstract: The present invention provides an architecture and method for increasing the performance and resource utilization of networked storage architectures by use of hardware-based storage element mapping. The architecture utilizes a customized programmable processing element to map host read or write commands to physical storage element commands. The present invention uses a plurality of data structures, such as tables, to map host read and write commands to physical storage elements. The hardware-based storage element mapping controller uses the tables, including a mapping segment descriptor table, to map from global address space addresses to physical storage element addresses.
    Type: Grant
    Filed: November 15, 2002
    Date of Patent: June 28, 2005
    Assignee: Aristos Logic Corporation
    Inventor: Robert Horn
  • Publication number: 20050102552
    Abstract: A method of volume rebuilding in a RAID for a networked storage system in which portions of a hard disk drive under rebuild are progressively made available to the system during the rebuild process as the portions are rebuilt. The impact of rebuild activity on system performance is controllable by allowing non-rebuild requests to throttle rebuild requests.
    Type: Application
    Filed: November 18, 2002
    Publication date: May 12, 2005
    Inventor: Robert Horn
  • Publication number: 20050091426
    Abstract: A multi-ported storage area network (SAN) controller system with command completion that utilizes optimal port selection. The system determines the optimal port for command completion based on criteria such as loop bandwidth utilization or port throughput maximization, and allows data and response information to occur via the optimal port regardless of the receiving port. This is accomplished through port aliasing (spoofing) of port identities, in which the receiving port identity is substituted into a sending port identity by a distributed control entity. In this way, any port within the SAN may return data or status to the originating host.
    Type: Application
    Filed: May 27, 2004
    Publication date: April 28, 2005
    Inventors: Robert Horn, Virgil Wilkins
  • Publication number: 20050066138
    Abstract: A storage element pending command queue prioritization system using multiple pending queues each assigned to a particular RAID command type. Pending commands from each of the queues are organized in such a way that lower priority commands are guaranteed a fixed amount of storage element bandwidth. Storage element throughput is optimized by limiting higher priority commands to a maximum service level and processing lower priority requests with the added storage element bandwidth, allowing lower priority requests to exceed their minimum service levels.
    Type: Application
    Filed: December 23, 2003
    Publication date: March 24, 2005
    Inventors: Robert Horn, Virgil Wilkins
  • Publication number: 20050066124
    Abstract: A method of efficiently preventing data loss, specifically a RAID 5 write hole, in data storage system by storing valid parity information at the storage controller level during data write operations. The method employs the use of redundant data structures that hold metadata specific to outstanding writes and parity information. The method uses the redundant data structures to recreate the write commands and data when a system failure occurs before the writes have completed.
    Type: Application
    Filed: December 23, 2003
    Publication date: March 24, 2005
    Inventors: Robert Horn, Virgil Wilkins
  • Publication number: 20050063216
    Abstract: A networked storage system controller architecture is capable of n-way distributed data redundancy using dynamically first-time allocated mirrored caches. Each storage controller has a cache mirror partition that may be used to mirror data in any other storage controller's dirty cache. As a storage controller receives a write request for a given volume it determines the owning storage controller for that volume. If another storage controller owns the volume requested, the receiving storage controller forwards the request to the owning storage controller. If no mirror has been previously established, the forwarding storage controller becomes the mirror. Thus, as data is received from the host, the receiving storage controller stores the data into its mirrored cache partition and copies the data to the owning storage controller.
    Type: Application
    Filed: September 23, 2004
    Publication date: March 24, 2005
    Inventors: Virgil Wilkins, Robert Horn
  • Publication number: 20050060477
    Abstract: An I/O controller having separate command and data paths, thereby eliminating the bandwidth used by the commands and thus increasing bandwidth available to the data buses. Additionally, the I/O controller uses multiple dedicated data paths, for example, dedicated distributed buses, and provides increased speed due to improved hardware integration. The I/O controller employs distributed processing methods that decouple the external microprocessor from much of the decision-making, thereby providing improved operating efficiency and thus more useable bandwidth at any given clock frequency. Accordingly, the I/O controller is capable of maximizing I/O operations (IOPS) on all I/O ports by functioning at the rate of I/O connections to hosts and storage elements without becoming a bottleneck.
    Type: Application
    Filed: August 27, 2004
    Publication date: March 17, 2005
    Inventors: Virgil Wilkins, Robert Horn
  • Publication number: 20050050240
    Abstract: An integrated I/O controller in an integrated circuit is provided for centralized data management. The integrated circuit includes a host interface, a disk interface, and a mapping controller implemented in hardware to speed data processing and provide fault tolerance as exemplified with RAID configurations. The mapping controller provides block mapping across a plurality of peripherals or disk drives in a disk array. The integrated I/O controller can be utilized in storage area network systems and network area storage systems as well as other networking systems or devices.
    Type: Application
    Filed: August 6, 2004
    Publication date: March 3, 2005
    Inventors: Virgil Wilkins, Robert Horn, Marc Acosta, Sanjay Mathur
  • Publication number: 20050050273
    Abstract: A RAID controller with decentralized transaction processor controllers and a decentralized cache allows for unlimited scalability in a networked storage system. Virtualization is provided through a map-and-forward function in which a virtual volume is mapped to its logical volumes at the controller level. Any controller in the system can map a request from any host port to any logical storage element. The network storage system provides a controller/virtualizer architecture for providing mirror consistency in a virtual storage environment in which different hosts may read or write to the same logical block address simultaneously. Each storage controller or virtualization engine controls access to a specific set of storage elements. One virtualizer engine is the coordinator, and monitors all write requests and looks for potential data conflicts. The coordinator alleviates conflicts by holding specific requests in a queue until execution of those request causes no data inconsistencies or cache incoherencies.
    Type: Application
    Filed: April 13, 2004
    Publication date: March 3, 2005
    Inventors: Robert Horn, Virgil Wilkins
  • Publication number: 20050050270
    Abstract: A method of predictive baseline volume profile creation for new volumes in a networked storage system and a system for dynamically reevaluating system performance and needs to create an optimized and efficient use of system resources by changing volume profiles as necessary. The system gathers statistical data and analyzes the information through algorithms to arrive at an optimal configuration for volume clusters. Clusters are then reallocated and reassigned to match the ideal system configuration for that point in time.
    Type: Application
    Filed: December 23, 2003
    Publication date: March 3, 2005
    Inventors: Robert Horn, Virgil Wilkins
  • Publication number: 20050050384
    Abstract: A dual parity hardware architecture that enables data to be read from each sector only once and performs both the P parity and Q parity from the single data source. The Q parity calculator provides parallel processing capabilities so that multiple parity operations are performed on the same sector simultaneously. The dual parity hardware architecture provides flexibility in restoring data, generating parity, and updating parity for differing data sector sizes.
    Type: Application
    Filed: August 25, 2004
    Publication date: March 3, 2005
    Inventor: Robert Horn