Abstract: An integrated circuit and method of manufacture therefore is provided having a semiconductor substrate with a semiconductor device with a dielectric layer over the semiconductor substrate. A conductor core fills the opening in the dielectric layer. An etch stop layer with a dielectric constant below 5.5 is formed over the first dielectric layer and conductor core. A second dielectric layer over the etch stop layer has an opening provided to the conductor core. A second conductor core fills the second opening and is connected to the first conductor core.

Abstract: The adhesion of a barrier or capping layer to a Cu or Cu alloy interconnect member is significantly enhanced by treating the exposed surface of the Cu or Cu alloy interconnect member, after CMP, in a reaction chamber with a plasma containing ammonia and nitrogen for a brief period of time to reduce the surface oxide and then introducing silane into the reaction chamber to deposit the barrier layer, e.g., silicon nitride, under high density plasma conditions in the presence of nitrogen. The presence of nitrogen during plasma oxide layer reduction and plasma barrier layer deposition significantly improves adhesion of the barrier layer to the Cu or Cu alloy surface.

Abstract: Bridging between nickel silicide layers on a gate electrode and source/drain regions along silicon nitride sidewall spacers is prevented by treating the exposed surfaces of the silicon nitride sidewall spacers with a plasma containing ammonia and nitrogen to create a clean surface region having increased nitrogen. Embodiments include treating the silicon nitride sidewall spacers with an ammonia and nitrogen plasma to reduce the refractive index of the surface region to less than about 1.95.

Abstract: An integrated circuit and manufacturing method therefor is provided having a semiconductor substrate with a semiconductor device. A device dielectric layer is formed on the semiconductor substrate, and a channel dielectric layer formed on the device dielectric layer has an opening formed therein. A barrier layer lines the channel opening and a conductor core fills the opening over the barrier layer. After planarization of the conductor core and the barrier layer, a plasma treatment is performed at 300° C. to reduce the conductor core material. A portion of a cap layer is deposited at 300° C. and the remainder is deposited at 400° C.

Abstract: A process for very low deposition rate plasma-enhanced chemical vapor deposition (PECVD) of nitride is provided. A nitride layer is used, for example, as a precursor for nitride spacers formed on the sidewalls of a polysilicon gate. The nitride layer may be produced in a PECVD chamber, using an increased flow rate of nitrogen applied to the chamber, an increased flow rate of molecular nitrogen, and a reduced flow rate of ammonia. The RF power is reduced, as well as the reactor pressure. This produces a nitride layer that exhibits improvements in density, refractive index, step coverage, and thickness non-unformity within a wafer and from wafer-to-wafer.

Abstract: A process for super low deposition rate plasma enhanced chemical vapor deposition (PECVD) of undoped oxide on a single station deposition is provided. A very thin PECVD oxide layer used, for instance, as an oxide liner between a polysilicon gate and a nitride spacer, may be produced in a PECVD chamber with a reduced flow rate of silane, nitrous oxide and molecular nitrogen. The deposition rate may be lowered to 20 angstroms/minute, for example, with this long deposition time providing a better process control. At the same time, the film is dense, silicon rich, highly compressive, provides excellent step coverage and acceptable thickness uniformity.

Abstract: In one embodiment, the present invention relates to a method of depositing a dielectric layer over a stacked interconnect structure, involving the steps of: providing a substrate having at least one stacked interconnect structure comprising at least one of an aluminum layer and an aluminum alloy layer; depositing the dielectric layer over the stacked interconnect structureunder a pressure from about 1 mTorr to about 6 mTorr, an O.sub.2 flow rate from about 110 sccm to about 130 sccm and a silane flow rate from about 52 sccm to about 60 sccm at a bias power from about 2500 W to about 3100 W,under a pressure from about 2 Torr to about 2.8 Torr, an N.sub.2 flow rate from about 7 l to about 11.5 l, an N.sub.2 O flow rate from about 1 l to about 2 l and a silane flow rate from about 250 sccm to about 300 sccm at a power from about 900 W to about 1300 W at a temperature from about 300.degree. C. to about 350.degree. C., orunder a pressure from about 2 Torr to about 2.8 Torr, an N.sub.

Abstract: A method for monitoring the temperature of a product wafer during thermal processing of the product wafer in an emissivity independent thermal processing system includes processing a test wafer in the emissivity independent thermal processing system that thermally processes the product wafer. The test wafer is pretreated before being thus placed in the thermal processing system. The test wafer is thermally processed following a substantially same thermal processing recipe as that used for thermal processing of the product wafers. After the thermal processing of the test wafer, a sheet resistance of the test wafer is measured. This sheet resistance is correlated to a wafer temperature at the test wafer that was achieved during the thermal processing of the test wafer.

Abstract: A method for monitoring the temperature of a product wafer during thermal processing of the product wafer in an emissivity independent thermal processing system includes processing a test wafer in the emissivity independent thermal processing system that thermally processes the product wafer. The test wafer is pretreated before being thus placed in the thermal processing system. The test wafer is thermally processed following a substantially same thermal processing recipe as that used for thermal processing of the product wafers. After the thermal processing of the test wafer, a sheet resistance of the test wafer is measured. This sheet resistance is correlated to a wafer temperature at the test wafer that was achieved during the thermal processing of the test wafer.