Abstract: A resolver having two inputs, one from a master pulse source and the other from a controlled device, and representative of the speed of that device is constituted by an up/down counter. An output is taken from the counter to provide a threshold so that when the counter is counting above that threshold a first output signal is derived which may be full on, and when the counter is counting below the threshold a second output is derived which may be full off. When the resolver is operating in normal steady state, the counter is counting up and down about the threshold, with the output alternating between full on and full off each time period.