Patents by Inventor Robert I. Wu

Robert I. Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor die with fuse window and a monitoring window over a structure which indicates fuse integrity
    Patent number: 8106476
    Abstract: According to one exemplary embodiment, a method for monitoring structural integrity of at least one fuse in semiconductor wafer, which includes at least one electrical monitoring structure, includes forming a monitoring window in a dielectric layer overlying the at least one electrical monitoring structure, where the monitoring window and a fuse window overlying the at least one fuse are, in one embodiment, formed in a same etch process. The method further includes performing at least one electrical measurement on the at least one electrical monitoring structure, wherein the at least one electrical measurement is utilized to monitor the structural integrity of the at least one fuse. A change in the at least one electrical measurement is utilized to indicate a change in the structural integrity of the at least one fuse. The at least one electrical monitoring structure can include, for example, a metal serpentine line and one or more metal combs.
    Type: Grant
    Filed: August 13, 2007
    Date of Patent: January 31, 2012
    Assignee: Broadcom Corporation
    Inventors: Robert I. Wu, Robert Lutze, Jung Kuan Wang, Voon Yean Ten, Liming Tsau
  • Method for monitoring fuse integrity in a semiconductor die and related structure
    Publication number: 20090045400
    Abstract: According to one exemplary embodiment, a method for monitoring structural integrity of at least one fuse in semiconductor wafer, which includes at least one electrical monitoring structure, includes forming a monitoring window in a dielectric layer overlying the at least one electrical monitoring structure, where the monitoring window and a fuse window overlying the at least one fuse are, in one embodiment, formed in a same etch process. The method further includes performing at least one electrical measurement on the at least one electrical monitoring structure, wherein the at least one electrical measurement is utilized to monitor the structural integrity of the at least one fuse. A change in the at least one electrical measurement is utilized to indicate a change in the structural integrity of the at least one fuse. The at least one electrical monitoring structure can include, for example, a metal serpentine line and one or more metal combs.
    Type: Application
    Filed: August 13, 2007
    Publication date: February 19, 2009
    Applicant: BROADCOM CORPORATION
    Inventors: Robert I. Wu, Robert Lutze, Jung Kuan Wang, Voon Yean Ten, Liming Tsau
  • Method for improving electroplating in sub-0.1um interconnects by adjusting immersion conditions
    Publication number: 20040245107
    Abstract: Embodiments of the invention provide methods of reducing electroplating defects by adjusting immersion conditions. For one embodiment, the immersion conditions are adjusted based upon characteristics of the substrate, including feature size. Additionally or alternatively, the immersion conditions may be adjusted based upon aspects of the electroplating process, including motion of the substrate upon immersion. Immersion conditions that may be adjusted in accordance with various embodiments of the invention include entry bias voltage/current, vertical immersion speed, and angle of immersion.
    Type: Application
    Filed: June 3, 2003
    Publication date: December 9, 2004
    Inventors: Guangli Che, Vinay B. Chikarmane, Christopher D. Thomas, Robert I. Wu, Daniel J. Zierath