Abstract: A switch apparatus for optimizing the transfer of data packets between a plurality of local area networks (LANs). Apparatus of the present invention are comprised of multiple independent controllers, e.g., a receive controller and a transmit controller, which share common resources including a first memory (a packet memory) which stores the data packets, a second memory (a descriptor memory) which stores pointers to the stored data packets, and buffered data paths (preferably using FIFO buffers). The independent controllers operate essentially concurrently for most tasks while interleaving their use of the shared resources. Consequently, embodiments of the present invention can simultaneously receive and transmit data across multiple LAN data ports (e.g., 28 Ethernet ports comprised of 10/100 and/or 10 Mbps ports).

Abstract: The present invention relates to a circuit board having a plurality of integrated circuits provided thereon, wherein each integrated circuit (IC) receives a common clocked input reference signal and outputs a dam signal. Each integrated circuit is provided with a de-skewing circuit which compensates for signal delays in the IC so as to synchronize the output data signal with the clocked input reference signal. The de-skewing circuit is operative to generate a simulated signal delay to the input signal which emulates the signal delays of the IC.

Abstract: Briefly, in accordance with one embodiment of the invention, an extendible local area network includes a hub station including a memory and at least one hub station segment. The hub station segment is adapted to be coupled to at least N other hub station segments by a bi-directional control signal bus, N being a positive integer. The hub station segment includes at least two ports, each of the ports being adapted to receive electrical signal packet transmissions from a remote station. The memory and the hub station segment are mutually coupled by a signal bus.

Abstract: An extendible, round robin, local area hub station network includes: at least two round robin hub station segments coupled so as to form a ring-shaped hub station segment signal path. One of the two hub station segments includes a master hub station segment adapted to provide control signals, such as electrical or optical signals, on the ring-shaped segment signal path to transfer control of round robin polling over the hub station network between any two hub station segments in the hub station network. The hub station segments are also mutually coupled by a signal bus.

Abstract: An integrated circuit includes a clock alignment circuit having a frequency synthesizer for receiving a reference clock signal at a lower frequency and for generating phases of an oscillator clock signal at a higher frequency. The oscillator clock signal phases drive a desired clock signal generating circuit that generates various phases of the desired clock signal. The desired clock signal phases are systematically compared to the reference clock signal. The phase of the desired clock signal that is determined to align with the reference clock signal is provided as the desired clock signal output from the integrated circuit such that there is no apparent time delay through the integrated circuit. In an alternate embodiment, a single phase of the desired clock signal is selected and a phase locked loop adjusts the oscillator in the frequency synthesizer to align the selected phase of the desired clock signal with the reference clock signal.

Abstract: A circuit includes both a frequency locked loop (FLL) and a phase locked loop (PLL) to control the frequency and phase of a controlled oscillator with respect to a data signal. The FLL includes a frequency setting register that provides a digital control word to a digital-to-analog converter for causing the frequency of the controlled oscillator to equal the frequency of the data signal. The PLL has a phase detector for causing the phase of the controlled oscillator to approximate the phase of the data signal. The inventive circuit also includes a lock detector for determining whether the phase error between the controlled oscillator and the data signal is constant. When phase lock is achieved, a counter is enabled to count a periodic reference signal and to produce an overflow signal when a given count is exceeded. The overflow signal is selectively coupled to the frequency setting register in order to reduce the phase difference between the controlled oscillator and the data signal.

Abstract: A hybrid ring network is disclosed having stations capable of transmitting and receiving packet and isochronous data. The ring stations include a latency adjustment buffer (LAB) which stores arriving packet data in one random access memory (PBUF) and both arriving packet and isochronous data in a separate random access memory (IBUF). For retransmission over the ring, packet data is read out only from the PBUF in accordance with the packet's retransmission priority. A LAB may be employed at a slave station and may be pre-programmed with a sufficient latency to compensate for an anticipated insertion or removal of a lobe, without changing the total latency of the ring. When a LAB is employed at a cycle master station the latency of the LAB is controlled by the total ring delay.