Abstract: Disclosed is a dual-receptacle carrier that is generally configured for attachment to a rollator or walker and that is configured to retain either a beverage or a mobile device, such as a cellular telephone. The device comprises a body, a base, and first and second opposing retention arm portions that are configured as a receptacle for a beverage. The first and second opposing retention arm portions and base include recesses that define a receptacle for an electronic device.

Abstract: The present invention is directed to injectable acid soluble collagen compositions comprising a neutralized solution of an acid soluble collagen, EDTA and preferably a polyol, wherein the composition is injectable at physiological pH and the acid soluble collagen polymerizes upon exposure to tissue. The invention is suitable for use in soft tissue augmentation, promoting soft tissue regeneration and coating medical implants and devices.

Abstract: In at least some examples, a computing node includes a processor and a local memory coupled to the processor. The computing node also includes a reflective memory bridge coupled to the processor. The reflective memory bridge maps to an incoming region of the local memory assigned to at least one external computing node and maps to an outgoing region of the local memory assigned to at least one external computing node.

Abstract: In at least some examples, a computing node includes a processor and a local memory coupled to the processor. The computing node also includes a reflective memory bridge coupled to the processor. The reflective memory bridge maps to an incoming region of the local memory assigned to at least one external computing node and maps to an outgoing region of the local memory assigned to at least one external computing node.

Abstract: The present invention is directed to injectable acid soluble collagen compositions comprising a neutralized solution of an acid soluble collagen, EDTA and preferably a polyol, wherein the composition is injectable at physiological pH and the acid soluble collagen polymerizes upon exposure to tissue. The invention is suitable for use in soft tissue augmentation, promoting soft tissue regeneration and coating medical implants and devices.

Abstract: The present invention is directed to injectable acid soluble collagen compositions comprising a neutralized solution of an acid soluble collagen, EDTA and preferably a polyol, wherein the composition is injectable at physiological pH and the acid soluble collagen polymerizes upon exposure to tissue. The invention is suitable for use in soft tissue augmentation, promoting soft tissue regeneration and coating medical implants and devices.

Abstract: In at least some examples, a computing node includes a processor and a local memory coupled to the processor. The computing node also includes a reflective memory bridge coupled to the processor. The reflective memory bridge maps to an incoming region of the local memory assigned to at least one external computing node and maps to an outgoing region of the local memory assigned to at least one external computing node.

Abstract: A state-retaining logic cell may include a plurality of inverters, an output node non-volatile (NVM) storage cell, and an input node NVM storage cell. The plurality of inverters may include a feed-forward inverter and a feed-back inverter disposed in a back-to-back arrangement. The output node NVM storage cell may include first and second terminals, where the first terminal is connected adjacent an output node of the feed-forward and the feed-back inverters, and the second terminal is connected to a programming rail. The input node NVM storage cell may include first and second terminals, where the first terminal is connected adjacent an input node of the feed-forward and the feed-back inverters, and the second terminal is connected to the programming rail.

Abstract: A CPU architecture is proposed which flexibly allocates chip resources among threads. Execution units (microcores) are arranged in a ring. Instruction fetch units (front-ends) deposit instructions sequentially into storage elements within the microcores. Multiple front-ends can each feed segments of the ring; each such segment is a “smart queue”. If, due to a sustained higher execution rate, a thread catches up to the next thread ahead of it, the slower thread steps aside and lets the faster thread play through. Other circumstances may lead to a thread consuming more than its usual share of resources, possibly even all of the microcores, for a time. The architecture has no instruction set dependencies; it is applicable to existing instruction set architectures and will speed up execution of them significantly as compared to conventional architectures.

Abstract: Techniques for updating data in a reflective memory region of a first memory device are described herein. In one example, a method for updating data in a reflective memory region of a first memory device includes receiving an indication that data is to be flushed from a cache device to the first memory device. The method also includes detecting a memory address corresponding to the data is within the reflective memory region of the first memory device and sending data from the cache device to the first memory device with a flush operation. Additionally, the method includes determining that the data received by the first memory device is modified data. Furthermore, the method includes sending the modified data to a second memory device in a second computing system.

Abstract: A nonvolatile memory device is writable to a high resistance state and a low resistance state. The nonvolatile memory device may be heated to at least a threshold temperature, based on application of an alternating current (AC) signal, and may be written based on application of a voltage bias.

Abstract: According to an example, a method for storage device reading may include receiving an input signal indicative of a period of oscillation of a ring oscillator coupled to a storage device of a plurality of storage devices, and measuring the period of oscillation of the ring oscillator by a time-to-digital circuit. The method for storage device reading may further include determining a value of data stored in the storage device based on the measurement.

Abstract: According to an example, a method for storage device write pulse control may include writing a storage device to a first polarity by driving a row address line (RAL) and a column address line (CAL) to an intermediate voltage level RCA for a cycle A. The RAL may be driven to a voltage level RB for a cycle B pulse duration, and the CAL may be maintained at RCA for the cycle B pulse duration. The RAL may be driven to a voltage level RC for a cycle C pulse duration, and the CAL may be driven to a voltage level CC for the cycle C pulse duration. The RAL may be driven to RCA, and the CAL may be driven to a voltage level CD for a cycle D pulse duration. The RAL may be maintained at RCA, and the CAL may be driven to RCA.

Abstract: According to an example, a method for storage device write pulse control may include writing a storage device to a first polarity by driving a row address line (RAL) and a column address line (CAL) to an intermediate voltage level RCA for a cycle A. The RAL may be driven to a voltage level RB for a cycle B pulse duration, and the CAL may be maintained at RCA for the cycle B pulse duration. The RAL may be driven to a voltage level RC for a cycle C pulse duration, and the CAL may be driven to a voltage level CC for the cycle C pulse duration. The RAL may be driven to RCA, and the CAL may be driven to a voltage level CD for a cycle D pulse duration. The RAL may be maintained at RCA, and the CAL may be driven to RCA.

Abstract: A nonvolatile memory device is writable to a high resistance state and a low resistance state. The nonvolatile memory device may be heated to at least a threshold temperature, based on application of an alternating current (AC) signal, and may be written based on application of a voltage bias.

Abstract: According to an example, a state-retaining logic cell may include a plurality of invertors. The state-retaining logic cell may further include an output node NVM storage cell connected adjacent an output node of one of the inverters.

Abstract: According to an example, a method for storage device reading may include receiving an input signal indicative of a period of oscillation of a ring oscillator coupled to a storage device of a plurality of storage devices, and measuring the period of oscillation of the ring oscillator by a time-to-digital circuit. The method for storage device reading may further include determining a value of data stored in the storage device based on the measurement.

Abstract: Techniques for updating data in a reflective memory region of a first memory device are described herein. In one example, a method for updating data in a reflective memory region of a first memory device includes receiving an indication that data is to be flushed from a cache device to the first memory device. The method also includes detecting a memory address corresponding to the data is within the reflective memory region of the first memory device and sending data from the cache device to the first memory device with a flush operation. Additionally, the method includes determining that the data received by the first memory device is modified data. Furthermore, the method includes sending the modified data to a second memory device in a second computing system.

Abstract: The present invention is directed to injectable acid soluble collagen compositions comprising a neutralized solution of an acid soluble collagen, EDTA and preferably a polyol, wherein the composition is injectable at physiological pH and the acid soluble collagen polymerizes upon exposure to tissue. The invention is suitable for use in soft tissue augmentation, promoting soft tissue regeneration and coating medical implants and devices.

Abstract: The present disclosure provides techniques for mapping large shared address spaces in a computing system. A method includes creating a physical address map for each node in a computing system. Each physical address map maps the memory of a node. Each physical address map is copied to a single address map to form a global address map that maps all memory of the computing system. The global address map is shared with all nodes in the computing system.