Abstract: A hardware controlled pipelined processor having an interpretive storage and multiple execution units employs interpretive storage "milli-instructions" and an interpretive execution "milli-mode". Additional hardware controlled instructions that are exclusively used in milli-mode may be added to provide additional controls or to improve performance (they augment the architected instruction set). Milli-mode routines intermingle milli-mode only instructions with architected instructions to implement complex functions. One milli-instruction called the DRAIN INSTRUCTION PIPELINE (DIP) causes the pipeline to drain selectively so the milli-programmer determines when and and what type of pipeline drain to perform. A DRAIN INSTRUCTION PIPELINE causes suspension of decoding until a selected event occurs. This DIP instruction includes options for suspending decoding until one of the following events have occurred: 1. all conceptually previous macro-instructions have completed; 2.

Abstract: Translation look aside buffer (TLB) hardware is provided in a central processor (CP) that receives the results of double-level address translations to eliminate the need for having shadow tables for the second-level in a virtual machine (VM) environment. Hardware is provided for indicating whether a requested address sent by the CP Instruction Execution (IE) unit for translation is a guest or host/native request, and for a guest request whether it is a real or virtual address. Intermediate translations for a double-level translation may or may not be inhibited from being loaded into the TLB. Guest entries may be purged from the TLB without disturbing any host entries. An accelerated preferred guest mode in the CP forces single-level translation hardware to translate each accelerated preferred guest request. A non-accelerated guest request may instead be translated by microcode. A limit check register is provided to check preferred guest addresses without causing performance degradation.

Abstract: The instruction register (IR), of a data processing system, stores a program instruction during at least an initial operation code decoding phase to initiate execution of the instruction. The IR (13) has a number of input gates in addition to the input gates from a program storing main storage device. The additional input gates respond to control or logic signals for gating information from the data flow hardware (40) to the instruction register.