Patents by Inventor Robert J. Chiu
Robert J. Chiu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7843015Abstract: An integrated circuit is provided. A gate dielectric is formed on a semiconductor substrate, and a gate is formed over the gate dielectric. A sidewall spacer is formed around the gate and a source/drain junction is formed in the semiconductor substrate using the sidewall spacer. A bottom silicide metal is deposited on the source/drain junction and then a top silicide metal is deposited on the bottom silicide metal. The bottom and top silicide metals are formed into their silicides. A dielectric layer is deposited above the semiconductor substrate and a contact is formed in the dielectric layer to the top silicide.Type: GrantFiled: September 15, 2005Date of Patent: November 30, 2010Assignee: GLOBALFOUNDRIES Inc.Inventors: Robert J. Chiu, Paul R. Besser, Simon Siu-Sing Chan, Jeffrey P. Patton, Austin C. Frenkel, Thorsten Kammler, Errol Todd Ryan
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Patent number: 7670915Abstract: A method of forming an integrated circuit with a semiconductor substrate is provided. A gate dielectric is formed on the semiconductor substrate, and a gate is formed on the gate dielectric. Source/drain junctions are formed in the semiconductor substrate. A silicide is formed on the source/drain junctions and on the gate. An interlayer dielectric having contact holes therein is formed above the semiconductor substrate. Contact liners are formed in the contact holes, and contacts are then formed over the contact liners. The contact liners are nitrides of the contact material, and formed at a temperature below the thermal budget for the silicide.Type: GrantFiled: March 1, 2004Date of Patent: March 2, 2010Assignee: Advanced Micro Devices, Inc.Inventors: Errol Todd Ryan, Paul R. Besser, Simon Siu-Sing Chan, Robert J. Chiu, Mehrdad Mahanpour, Minh Van Ngo
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Publication number: 20090050471Abstract: A process of forming an electronic device can include depositing a first layer over a substrate and depositing a second layer over the first layer. In one embodiment, depositing the first layer is performed at a first alternating current (“AC”) power, and depositing the second layer is performed at a second AC power that is different from the first AC power. In another embodiment, the first layer is formed by a physical vapor deposition technique at a first power sufficient to remove the insulating layer using first metal ions, wherein the first layer includes an overhanging portion extending over the bottom of the opening. In a further embodiment, the second layer is formed by the physical vapor deposition technique using second metal ions and a second power sufficient to reduce a lateral dimension of the overhanging portion.Type: ApplicationFiled: August 24, 2007Publication date: February 26, 2009Applicant: SPANSION LLCInventors: Robert J. Chiu, Connie Pin-Chin Wang, Minh Van Ngo, Simon S. Chan
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Patent number: 7307322Abstract: A structure of an integrated circuit is provided. A gate dielectric is formed on a semiconductor substrate, and a gate is formed over a gate dielectric on the semiconductor substrate. Source/drain junctions are formed in the semiconductor substrate. Ultra-uniform suicides are formed on the source/drain junctions, and a dielectric layer is deposited above the semiconductor substrate. Contacts are then formed in the dielectric layer to the ultra-uniform silicides.Type: GrantFiled: October 17, 2005Date of Patent: December 11, 2007Assignee: Adavnced Micro Devices, Inc.Inventors: Robert J. Chiu, Jeffrey P. Patton, Paul R. Besser, Minh Van Ngo
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Patent number: 7151020Abstract: A method of forming an integrated circuit with a semiconductor substrate is provided. A gate dielectric is formed on the semiconductor substrate, and a gate is formed on the gate dielectric. Source/drain junctions are formed in the semiconductor substrate. A transition metal layer is formed on the source/drain junctions and on the gate. An interlayer dielectric is formed above the semiconductor substrate. Contacts are then formed in the interlayer dielectric, whereby a silicide is formed from the transition metal layer at a temperature no higher than the maximum temperature at which the interlayer dielectric and the contacts are formed.Type: GrantFiled: May 4, 2004Date of Patent: December 19, 2006Assignee: Advanced Micro Devices, Inc.Inventors: Jeffrey P. Patton, Austin C. Frenkel, Thorsten Kammler, Robert J. Chiu, Errol Todd Ryan, Darin A. Chan, Paul R. Besser, Paul L. King, Minh Van Ngo
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Patent number: 7049666Abstract: A method of forming an integrated circuit with a semiconductor substrate is provided. A gate dielectric is formed on the semiconductor substrate, and a gate is formed on the gate dielectric. Source/drain junctions are formed in the semiconductor substrate. A thin insulating layer is formed over the source/drain junctions. A silicide is formed on the thin insulating layer and on the gate. An interlayer dielectric is deposited above the semiconductor substrate. Contacts are then formed in the interlayer dielectric to the silicide.Type: GrantFiled: June 1, 2004Date of Patent: May 23, 2006Assignee: Advanced Micro Devices, Inc.Inventors: Robert J. Chiu, Jeffrey P. Patton, Paul R. Besser, Minh Van Ngo
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Patent number: 7005376Abstract: A method of forming and a structure of an integrated circuit are provided. A gate dielectric is formed on a semiconductor substrate, and a gate is formed over a gate dielectric on the semiconductor substrate. Source/drain junctions are formed in the semiconductor substrate. Ultra-uniform silicides are formed on the source/drain junctions, and a dielectric layer is deposited above the semiconductor substrate. Contacts are then formed in the dielectric layer to the ultra-uniform silicides.Type: GrantFiled: July 7, 2003Date of Patent: February 28, 2006Assignee: Advanced Micro Devices, Inc.Inventors: Robert J. Chiu, Jeffrey P. Patton, Paul R. Besser, Minh Van Ngo
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Patent number: 7005357Abstract: A method of forming an integrated circuit with a semiconductor substrate is provided. A gate dielectric is formed on the semiconductor substrate, and a gate is formed on the gate dielectric. Source/drain junctions are formed in the semiconductor substrate. A sidewall spacer is formed around the gate using a low power plasma enhanced chemical vapor deposition process A silicide is formed on the source/drain junctions and on the gate, and an interlayer dielectric is deposited above the semiconductor substrate. Contacts are then formed in the interlayer dielectric to the silicide.Type: GrantFiled: January 12, 2004Date of Patent: February 28, 2006Assignee: Advanced Micro Devices, Inc.Inventors: Minh Van Ngo, Simon Siu-Sing Chan, Paul R. Besser, Paul L. King, Errol Todd Ryan, Robert J. Chiu
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Patent number: 6969678Abstract: A method of forming an integrated circuit, and an integrated circuit, are provided. A gate dielectric is formed on a semiconductor substrate, and a gate is formed over the gate dielectric. A sidewall spacer is formed around the gate and a source/drain junction is formed in the semiconductor substrate using the sidewall spacer. A bottom silicide metal is deposited on the source/drain junction and then a top silicide metal is deposited on the bottom silicide metal. The bottom and top silicide metals are formed into their silicides. A dielectric layer is deposited above the semiconductor substrate and a contact is formed in the dielectric layer to the top silicide.Type: GrantFiled: November 3, 2003Date of Patent: November 29, 2005Assignee: Advanced Micro Devices, Inc.Inventors: Robert J. Chiu, Paul R. Besser, Simon Siu-Sing Chan, Jeffrey P. Patton, Austin C. Frenkel, Thorsten Kammler, Errol Todd Ryan
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Patent number: 6576548Abstract: Reliable contacts/vias are formed by sputter etching to flare exposed edges of an opening formed in a dielectric layer, depositing a composite barrier layer and then filling the opening with tungsten at a low deposition rate. The resulting contact/via exhibits significantly reduced porosity and contact resistance. Embodiments include sputter etching to incline the edges of an opening formed in an oxide dielectric layer, e.g., a silicon oxide derived from TEOS or BPSG, at an angle of about 83° to about 86°, depositing a thin layer of Ti, e.g., at a thickness of about 250 Å to about 350 Å, depositing at least one layer of titanium nitride, e.g., three layers of titanium nitride, at a total thickness of about 130 Å to about 170 Å, and then depositing tungsten at a deposition rate of about 1,900 to about 2,300 Å/min to fill the opening.Type: GrantFiled: February 22, 2002Date of Patent: June 10, 2003Assignee: Advanced Micro Devices, Inc.Inventors: Amy Tu, Minh Van Ngo, Austin Frenkel, Robert J. Chiu, Jeff Erhardt
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Patent number: 6171737Abstract: A low cost technique for detecting defects in photolithography processes in a submicron integrated circuit manufacturing environment combines use of a reusable test wafer with in-line processing to monitor defects using a pattern comparator system. A reusable test wafer having an oxide layer overlying a silicon substrate and having a thickness corresponding to a minimum reflectance for an exposure wavelength used for photolithography is patterned using a prescribed photolithographic fabrication process to form a repetitive pattern according to a prescribed design product rule. The pattern is formed using a reticle having a repetitive pattern array with a similar design rule as the product to be developed by the lithography processes. The patterned test wafer is then inspected using image-based inspection techniques, where the image has high resolution pixels of preferably 0.25 microns per pixel.Type: GrantFiled: February 3, 1998Date of Patent: January 9, 2001Assignee: Advanced Micro Devices, Inc.Inventors: Khoi A. Phan, Shobhana R. Punjabi, Robert J. Chiu, Bhanwar Singh