Abstract: A missile simulator training apparatus (44) for pilot training of an aircraft of the type having at least one missile station, including a pre-launch module (10) for substantially simulating the pre-launch functions of a missile in response to data received from the aircraft. The apparatus also includes an inert factor formed missile body (32), thereby providing the apparatus with static and aerodynamic loads equivalent to that of an actual missile. The apparatus further includes a data link and data capture module (46) for recording all data transactions between the apparatus and the aircraft for post-flight analysis of aircraft and pilot performance.

Abstract: An apparatus (10) for testing an operational status of a missile interface system includes a portable control unit (16) having an interface panel (28). The interface panel (28) has a plurality of umbilical ports adapted to receive data from a plurality of missile stations (12) via a corresponding plurality of umbilical cables (18). The interface panel (28) is further includes a coaxial port (40), adapted to receive data from a radar trap (22) via a coaxial cable (20). The apparatus further includes a fixture assembly (116) having a main body portion (120). The main body portion (120) has a channel (122) through which a first end of the umbilical cable (18) is allowed to pass. The fixture assembly (116) is adapted to be releasably mounted to a missile station (12).

Abstract: Transmitting and receiving apparatus for transmitting data which includes a purged extended Golay (22,7) code encoder at the transmitter for encoding digital data into constant weight unbalanced codewords representative of the digital data. The constant weight unbalanced codewords contain error correction bits and are preferably transmitted as balanced codewords. When the receiver decodes the original digital data, improved tracking and acquisition of the transmitted data is achieved.

Abstract: Transmitting and receiving apparatus for transmitting data includes a purged code encoder at the transmitter for encoding digital data into constant weight unbalanced codewords representative of the digital data. The constant weight unbalanced codewords containing error correction bits are preferably transmitted as balanced codewords and are decoded at the receiver employing Golay decoders or algebraic decoders to recover the original digital data without the requirement of a large number of matched filter previously employed for decoding.

Abstract: A novel maximum likelihood sequence detector is provided for decoding linear cyclic error correction codes. The detector comprises one cyclic correlator for each two shaft sets of the code which have weights greater than one, and a serial correlator for detecting the shift sets of all zero's and all one's. The number of cyclic correlators required to decode linear codes is reduced to less than half the number of shift sets which define all the codewords instead of half the number of codewords where the number of shift sets is always less than the number of codewords.

Abstract: A decoder for forward-error-correcting (FEC) convolutional codes. The decoder uses the Viterbi algorithm for decoding the rate 1/2, constraint length 7 code with generator polynomials x.sup.6 +x.sup.5 +x.sup.3 +x.sup.2 +1, and x.sup.6 +x.sup.3 +x.sup.2 +x+1. The architecture of the instant decoder is appropriate for implementation on a single, monolithic VLSI integrated circuit chip and includes a branch metric calculator circuit which produces output signals representative of input symbol signals. These output signals are supplied to a metric update circuit which evaluates the signals from the calculator circuit and provides decisions to a path update circuit which converges the signals thereto and the output signals of which are evaluated by a majority vote circuit which produces data output signals representative of data input signals.

Abstract: A novel interleaver-de-interleaver is provided which is adapted to store bits of a data stream after being error encoded. The data bits are stored in a random access memory in addresses identifiable by an array of columns and rows. The interleaver comprises address pointer means and logic for reading the data bits out of the memory addresses in a predetermined reordered sequence to provide a quasi-random pattern sequence of data bits which when transmitted are substantially immune to periodic bursts of radio frequency interference signals.