Abstract: In a system having independently-clocked job-performing circuits (e.g., payload processors) and independently-clocked job-ordering circuits (e.g., request and payload suppliers), coordinating mechanisms are provided for coordinating exchanges between the independently-clocked circuits. The coordinating mechanisms include those that use transmitted time-stamps for scheduling contention-free performances within the job-performing circuits of requested jobs. The coordinating mechanisms additionally or alternatively include static and dynamic rate constraining means that are configured to prevent a faster-clocked one of the independently-clocked circuits from overwhelming a more slowly-clocked other of the independently-clocked circuits. In one implementation, independently-clocked telecommunication-shelves house a distributed set of line cards and switch cards.

Abstract: In a system having independently-clocked job-performing circuits (e.g., payload processors) and independently-clocked job-ordering circuits (e.g., request and payload suppliers), coordinating mechanisms are provided for coordinating exchanges between the independently-clocked circuits. The coordinating mechanisms include those that use transmitted time-stamps for scheduling contention-free performances within the job-performing circuits of requested jobs. The coordinating mechanisms additionally or alternatively include static and dynamic rate constraining means that are configured to prevent a faster-clocked one of the independently-clocked circuits from overwhelming a more slowly-clocked other of the independently-clocked circuits. In one implementation, independently-clocked telecommunication-shelves house a distributed set of line cards and switch cards.

Abstract: An input port for a network switch includes a cell buffer for receiving incoming unicast and multicast cells and for writing each cell into an internal cell memory. The cell buffer thereafter forwards each unicast cell from the cell memory to one network switch output port and forwards a separate copy of each multicast cell to each of several network switch output ports. When the cell buffer writes a unicast cell to the cell memory, it sends a pointer to the storage location of the unicast cell to a queue manager. When the cell buffer writes a multicast cell to the cell memory, it sends several pointers to the queue manager, one for each output port that is to receive a copy of the multicast cell, with each pointer pointing not to the multicast cell's storage location but to an empty storage location in the cell memory. The cell buffer also maintains a database relating each pointer it sent to the queue manager to an actual storage location of a unicast or multicast cell.

Abstract: A digital switching system comprises: (a) a line card layer containing a plurality of real or virtual line cards; (b) a switch card layer containing a plurality of real or virtual switch cards; and (c) an interface layer interposed between the line card layer and the switch card layer for providing serialization support services so that one or more of the line cards and switch cards can be operatively and conveniently disposed in a first shelf or on a first backplane that is spaced apart from a second shelf or from a second backplane supporting others of the line cards and/or switch cards. Such an arrangement allows for scalable expansion of the switching system in terms of number of lines served and/or transmission rates served. The flexibility of the system is owed in part to payload data being carried within payload-carrying regions of so-called ZCell signals as the payload data moves between the line card layer and the switch fabric layer.

Abstract: An input or output switch port for a network switch converts each incoming packet into a cell sequence stores each cell in a cell memory. The switch port includes a traffic manager for queuing cells for departure from the cell memory and then signaling the cell memory to read out and forward cells in the order they are queued. The traffic manager selectively queues cells for departure on either a cell-by-cell or sequence-by-sequence basis. When cells are queued for departure on a cell-by-cell basis, cells of two or more sequences may be alternately read out and forwarded from the cell memory. Thus cells of different sequences may be interleaved with one another as they depart the cell memory. When a cell sequence is queued on a sequence-by-sequence basis all of its cells are read out of the cell memory and forwarded as a contiguous sequence and are not interleaved with cells of other sequences of the same departure queue.

Abstract: A network switch port includes a cell memory, a queuing system, a data path controller and an output buffer. The data path controller stores incoming cells derived from network data transmissions in the cell memory. The queuing system generates the cell memory address of each stored cell when the cell is to be forwarded from the cell memory, and the data path controller appends the cell memory address of that cell to a linked list of addresses of cells to be forwarded from the memory. When the linked list is not empty, the data path controller forwards cells from the cell memory to the output buffer in the order that their cell memory addresses were appended to the linked list. The output buffer stores and then sequentially forwards the cells outward from the switch port to a receiving network component which store them in a cell buffer until it can forward them elsewhere.

Abstract: A traffic manager for a network switch input or output port stores incoming cells in a cell memory and later sends each cell out of its cell memory toward one of a set of forwarding resources such as, for example, another switch port or an output bus. Data in each cell references the particular forwarding resource to receive the cell. Each cell is assigned to one of several flow queues such that all cells assigned to the same flow queue are to be sent to the same forwarding resource. The traffic manager maintains a separate virtual output queue (VOQ) associated with each forwarding resource and periodically loads a flow queue (FQ) number identifying each flow queue into the VOQ associated with the forwarding resource that is to receive the cells assigned to that FQ. The traffic manager also periodically shifts an FQ ID out of each non-empty VOQ and forwards the longest-stored cell assigned to that FQ from the cell memory toward its intended forwarding resource.

Abstract: A network switch port includes a cell memory, a queuing system, a data path controller and an output buffer. The data path controller stores incoming cells derived from network data transmissions in the cell memory. The queuing system generates the cell memory address of each stored cell when the cell is to be forwarded from the cell memory, and the data path controller appends the cell memory address of that cell to a linked list of addresses of cells to be forwarded from the memory. When the linked list is not empty, the data path controller forwards cells from the cell memory to the output buffer in the order that their cell memory addresses were appended to the linked list. The output buffer stores and then sequentially forwards the cells outward from the switch port to a receiving network component which store them in a cell buffer until it can forward them elsewhere.

Abstract: A traffic manager for a network switch port stores incoming cells in a cell memory and later forwards them out of the cell memory and the switch port. Each cell is assigned to one of several flow queues and each flow queue has an assigned minimum forwarding bandwidth with which cells of that flow queue must be forwarded from the cell memory and has an assigned maximum bandwidth with which cells of that flow queue may be forwarded. When any flow queue is active (i.e., when it has cells currently stored in the cell memory), the traffic manager allocates a sufficient amount of the switch port's available cell forwarding bandwidth to each active flow queue so that cells of that flow queue are forwarded with at least the flow queue's assigned minimum bandwidth.

Abstract: A method for automatic early packet discard mode enabling early packet discard on a cell switching network is disclosed. The method includes the steps of counting every non-end of the frame data cell that arrives on a network connection, comparing the number of non-end of the frame data cell to a predetermined threshold value to determine whether the traffic arriving on the network connection is a frame based traffic and enabling early packet discard if the traffic is frame based.

Abstract: A traffic manager for a network switch port includes a buffer memory and a buffer manager for writing incoming cells into the buffer memory and for thereafter reading the cells out of the buffer memory and forwarding them. The traffic manager also includes a queue manager for determining an order in which the buffer manager is to forward a set of cells stored in the buffer memory. The queue manager supplies the buffer manager with a sequence of pointers, each pointer referencing a separate cell of the set of cells, with the sequence of pointers being ordered to indicate an order in which the buffer manager is to forward the set of cells. After receiving the pointer sequence, the buffer manager changes the order of pointers in the pointer sequence to optimize a rate at which it can read the cells out of the buffer memory.

Abstract: A traffic manager for a network switch port includes a buffer memory and a buffer manager for writing incoming cells into the buffer memory and for thereafter reading the cells out of the buffer memory and forwarding them. The traffic manager also includes a queue manager for determining an order in which the buffer manager is to forward a set of cells stored in the buffer memory. The queue manager supplies the buffer manager with a sequence of pointers, each pointer referencing a separate cell of the set of cells, with the sequence of pointers being ordered to indicate an order in which the buffer manager is to forward the set of cells. After receiving the pointer sequence, the buffer manager changes the order of pointers in the pointer sequence to optimize a rate at which it can read the cells out of the buffer memory.

Abstract: An input port for a network switch includes a cell buffer for receiving incoming unicast and multicast cells and for writing each cell into an internal cell memory. The cell buffer thereafter forwards each unicast cell from the cell memory to one network switch output port and forwards a separate copy of each multicast cell to each of several network switch output ports. When the cell buffer writes a unicast cell to the cell memory, it sends a pointer to the storage location of the unicast cell to a queue manager. When the cell buffer writes a multicast cell to the cell memory, it sends several pointers to the queue manager, one for each output port that is to receive a copy of the multicast cell, with each pointer pointing not to the multicast cell's storage location but to an empty storage location in the cell memory. The cell buffer also maintains a database relating each pointer it sent to the queue manager to an actual storage location of a unicast or multicast cell.

Abstract: A traffic manager for a network switch input or output port stores incoming cells in a cell memory and later sends each cell out of its cell memory toward one of a set of forwarding resources such as, for example, another switch port or an output bus. Data in each cell references the particular forwarding resource to receive the cell. Each cell is assigned to one of several flow queues such that all cells assigned to the same flow queue are to be sent to the same forwarding resource. The traffic manager maintains a separate virtual output queue (VOQ) associated with each forwarding resource and periodically loads a flow queue (FQ) number identifying each flow queue into the VOQ associated with the forwarding resource that is to receive the cells assigned to that FQ. The traffic manager also periodically shifts an FQ ID out of each non-empty VOQ and forwards the longest-stored cell assigned to that FQ from the cell memory toward its intended forwarding resource.

Abstract: A traffic manager for a network switch port stores incoming cells in a cell memory and later forwards them out of the cell memory and the switch port. Each cell is assigned to one of several flow queues and each flow queue has an assigned minimum forwarding bandwidth with which cells of that flow queue must be forwarded from the cell memory and has an assigned maximum bandwidth with which cells of that flow queue may be forwarded. When any flow queue is active (i.e., when it has cells currently stored in the cell memory), the traffic manager allocates a sufficient amount of the switch port's available cell forwarding bandwidth to each active flow queue so that cells of that flow queue are forwarded with at least the flow queue's assigned minimum bandwidth.

Abstract: An input or output switch port for a network switch converts each incoming packet into a cell sequence stores each cell in a cell memory. The switch port includes a traffic manager for queuing cells for departure from the cell memory and then signaling the cell memory to read out and forward cells in the order they are queued. The traffic manager selectively queues cells for departure on either a cell-by-cell or sequence-by-sequence basis. When cells are queued for departure on a cell-by-cell basis, cells of two or more sequences may be alternately read out and forwarded from the cell memory. Thus cells of different sequences may be interleaved with one another as they depart the cell memory. When a cell sequence is queued on a sequence-by-sequence basis all of its cells are read out of the cell memory and forwarded as a contiguous sequence and are not interleaved with cells of other sequences of the same departure queue.

Abstract: A pipelined processor in which the decoder can consume a portion of an instruction and hold that portion in sub-field shadow registers while retrieving the remainder of the instruction in a subsequent cycle or cycles. Each byte in a prefetch buffer is individually tagged such that the decoder can clear individual bytes in the prefetch buffer in order to allow additional instruction bytes to be prefetched before the current instruction is completely consumed and decoded by the decode stage. This allows for an optimal buffer size that is less than the maximum possible instruction length but large enough to hold a complete copy of the vast majority of instructions.

Abstract: A system and method for assigning departure timeslots to arrival data in an ATM switch is described. The departure timeslots are assigned to arrival data when no departure data is pending or when arrival data has a higher priority than pending departure data.

Abstract: Memory requests are pipelined to an external memory by forming a memory address during the same clock cycle that the associated instruction is executed, issuing a ready signal during the clock cycle that precedes the clock cycle in which information is output from an external memory, and directing information received from the external memory to a register file during the same clock cycle that the information is received. In addition, when an instruction requires the information that was requested by the previous instruction, the information is directed to an arithmetic logic unit (ALU) during the same clock cycle that the information is received. As a result, the cycle time required to retrieve information stored in a DRAM can be substantially reduced.

Abstract: The power consumed by a cache memory when the cache is read is reduced by utilizing a cache access circuit to prevent the cache from being read when the information stored in the cache is invalid, such as when the processor is powered up, reset by a user, or an invalidation bit is set.