Abstract: The present invention relates to semiconductor devices, including multi-chip semiconductor devices, and methods of coupling semiconductor devices. In a particular embodiment, the semiconductor device is a multi-chip semiconductor that comprises a first semiconductor device and a second semiconductor device. The first semiconductor device has a first surface. The first surface contains a first ridge alignment member and a second ridge alignment member, the first and second ridge alignment members forming a receiving area between the first and second ridge alignment members. The second semiconductor device has a second surface, the second surface containing a third ridge alignment member, the second semiconductor device positioned such that at least a portion of the third ridge alignment member is located within the receiving area of the first semiconductor device.

Abstract: An apparatus and method for a sensing circuit for cancelling an offset voltage. Specifically, in one embodiment, a CMOS inverter amplifier amplifies an input signal present at an input node. A resistive feedback circuit is coupled to the CMOS inverter amplifier for cancelling an offset voltage that is associated with the CMOS inverter amplifier. This is accomplished by biasing the CMOS inverter amplifier to its threshold voltage. A bias circuit is coupled to the resistive feedback circuit for biasing MOSFET transistors in the resistive feedback circuit at a subthreshold conduction region. As such, the resistive feedback circuit presents a high impedance to the input node. A clamping circuit, coupled to the resistive feedback circuit, maintains operation of the transistors in the resistive feedback circuit in the subthreshold conduction region.

Abstract: A bi-directional communication system and transceiver configuration are described, which employ a bi-directional reference to account for both common-mode and differential noise introduced at either end of a bi-directional communication channel. Some implementations exploit the techniques described in a bi-directional chip-to-chip communication scheme. In some implementations, the advantages of bi-directional reference techniques described herein are obtained while pre-distortion of transmitted signals is employed to compensate for intersymbol interference (ISI) in a communications channel.

Abstract: One embodiment of the present invention provides a system that uses electrostatic forces to align semiconductor chips relative to each other. The system operates by fabricating a first set of conductors on the top surface of a first chip and fabricating a corresponding second set of conductors on the top surface of a second chip. To align the chips, the system electrically charges the first set of conductors and the second set of conductors. The system also places the first chip face-to-face with the second chip, so that the first set of conductors is in close proximity to the second set of conductors. This allows electrostatic forces between the first set of conductors and the second set of conductors to bring the first chip into alignment with the second chip and to hold them in place.

Abstract: A clock interpolation circuit for setting and controlling a phase of an output clock that is derived from an interpolation of multiple input clocks. Interpolation is performed by capacitively weighting the multiple clocks. A select and control circuit provides the ability to select different capacitance values to control the weighting. An optional buffer stage is also provided to sharpen the edge transitions of the interpolated clock.

Abstract: One embodiment of the present invention provides a system that electronically aligns pads on different semiconductor chips to facilitate communication between the semiconductor chips through capacitive coupling. The system operates by measuring an alignment between a first chip and a second chip, wherein the first chip is situated face-to-face with the second chip so that transmitter pads on the first chip are capacitively coupled with receiver pads on the second chip. Next, the system uses the measured alignment to associate transmitter pads on the first chip with proximate receiver pads on the second chip. The system then selectively routes data signals to transmitter pads on the first chip so that the data signals are communicated through capacitive coupling to intended receiver pads in the second chip that are proximate to the transmitter pads.

Abstract: The present invention relates to an integrated circuit device and method of adjusting capacitance of a node of an integrated circuit In one embodiment, the device comprises a first digital input, a first parasitic capacitance block, a first output, a second digital input, a second parasitic capacitance block and a second output. The first parasitic capacitance block includes an inverter, a variable capacitance element, and a wire capacitance element. The first parasitic capacitance block has a capacitance that is a function of the first digital input. The first output is responsive to the first parasitic capacitance block, and the second output is responsive to the second parasitic capacitance block.

Abstract: The present invention relates to an integrated circuit device and method of adjusting capacitance of a node of an integrated circuit In one embodiment, the device comprises a first digital input, a first parasitic capacitance block, a first output, a second digital input, a second parasitic capacitance block and a second output. The first parasitic capacitance block includes an inverter, a variable capacitance element, and a wire capacitance element. The first parasitic capacitance block has a capacitance that is a function of the first digital input. The first output is responsive to the first parasitic capacitance block, and the second output is responsive to the second parasitic capacitance block.

Abstract: The present invention relates to semiconductor devices, including multi-chip semiconductor devices, and methods of coupling semiconductor devices. In a particular embodiment, the semiconductor device is a multi-chip semiconductor that comprises a first semiconductor device and a second semiconductor device. The first semiconductor device has a first surface. The first surface contains a first ridge alignment member and a second ridge alignment member, the first and second ridge alignment members forming a receiving area between the first and second ridge alignment members. The second semiconductor device has a second surface, the second surface containing a third ridge alignment member, the second semiconductor device positioned such that at least a portion of the third ridge alignment member is located within the receiving area of the first semiconductor device.

Abstract: A clamping circuit which is connected to each long line, preferably adjacent the receiver. The clamping circuit biases the long line at the trigger threshold of the receiver. Thus, instead of amplifying the signal as a repeater will do, the present invention clamps the line to the threshold, thus allowing a faster response since the line doesn't have to be charged or discharged from a lower or higher level to the threshold. This thus speeds up the transition at the receiver without requiring a repeater or a keeper.

Abstract: One embodiment of the present invention provides resistor within an integrated circuit with a substantially linear resistance. This resistor includes a diode-connected transistor coupled in parallel with a current-source-connected transistor, so that a nonlinear resistance of the diode-connected transistor combines with a nonlinear resistance of the current-source-connected transistor to produce a substantially linear combined resistance. It also includes selection circuit that is configured to selectively deactivate the resistor by deactivating the diode-connected transistor and the current-source-connected transistor. This selection circuit provides a range of possible resistance values, and thus enables the resistance to be quickly switched on and off to allow for use in a high-speed driver circuit.

Abstract: The present invention relates to semiconductor devices, including multi-chip semiconductor devices, and methods of coupling semiconductor devices. In a particular embodiment, the semiconductor device is a multi-chip semiconductor that comprises a first semiconductor device and a second semiconductor device. The first semiconductor device has a first surface. The first surface contains a first ridge alignment member and a second ridge alignment member, the first and second ridge alignment members forming a receiving area between the first and second ridge alignment members. The second semiconductor device has a second surface, the second surface containing a third ridge alignment member, the second semiconductor device positioned such that at least a portion of the third ridge alignment member is located within the receiving area of the first semiconductor device.

Abstract: A bi-directional communication system and transceiver configuration are described, which employ a bidirectional reference to account for both common-mode and differential noise introduced at either end of a bidirectional communication channel. Some implementations exploit the techniques described in a bi-directional chip-to-chip communication scheme. In some implementations, the advantages of bi-directional reference techniques described herein are obtained while pre-distortion of transmitted signals is employed to compensate for intersymbol interference (ISI) in a communications channel.

Abstract: One embodiment of the present invention provides a system for amplifying an input signal received from a capacitive sensor. The system includes an input for receiving an input signal from the capacitive sensor and an amplifier that amplifies the input signal to produce an output signal. This amplifier includes a pull-up circuit that pulls the output signal up to a high voltage when the input signal exceeds a threshold voltage. It also includes a pull-down circuit that pulls the output signal down to a low voltage when the input signal falls below the threshold voltage. After the output signal is pulled up to the high voltage, the pull-up circuit enters a refractory state in which the pull-up circuit uses a limited current, and the pull-down circuit enters a receptive state in which the pull-down circuit is sensitized to react to small changes in the input signal.

Abstract: A clock interpolation circuit for setting and controlling a phase of an output clock that is derived from an interpolation of multiple input clocks. Interpolation is performed by capacitively weighting the multiple clocks. A select and control circuit provides the ability to select different capacitance values to control the weighting. An optional buffer stage is also provided to sharpen the edge transitions of the interpolated clock.

Abstract: A sense amplifier having dual differential inputs configured to accept differential analog input voltages. The differential analog input voltages are fused to determine a weighted signal digitally representative of the differential analog input voltages. An input offset voltage cancellation circuit may be coupled to the sense amplifier to reduce an input offset voltage of the sense amplifier.

Abstract: In an input receiver circuit includes a signal input for receiving a signal input to a chip, a chip output for supplying a buffered signal to circuitry on the chip and a positive feedback circuit coupled between the chip output and the signal input. The positive feedback circuit might comprise a first inverter having an input coupled to the signal input, a second inverter having an input coupled to an output of the first inverter, wherein an output of the second inverter provides the chip output, and an inverting buffer having an input coupled to the output of the second inverter and an output coupled to the signal input.

Abstract: An improved loop filter contains an active device which maintains a phase lock loop's zero frequency to bandwidth ratio substantially constant with changes in the incoming frequency. It does this by maintaining filter resistance proportional to the inverse square root of the filter current, and without requiring duplicates of circuit elements. Constructed in this way a phase lock loop can be achieved which has a wide operating frequency range and low tracking jitter.

Abstract: A high speed self-terminated output driver includes an array of resistive drivers that are pulse-activated in succession to process a corresponding succession of data bits. The output driver thus synthesizes an output waveform which behaves similar to a single resistive drive element responding to the non-bandlimited input signal. In various embodiment, the output driver provides for digitally programmable output impedance and pre-distortion levels.

Abstract: Method and circuitry for improving noise immunity of differential data channels that use a shared reference channel by substantially matching their respective noise transfer functions. Any combination of various circuit parameters at the reference channel including termination resistance R, channel impedance Zo, and parasitic inductance L are scaled to substantially match the noise transfer function of the reference channel to that of the data channels.