Patents by Inventor Robert J. Dupcak
Robert J. Dupcak has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7868706Abstract: An oscillator device includes a plurality of stages. Each stage is a monostable stage having a delay path, whereby a signal transition of a designated type (rising or falling) at the input of the delay path results in a signal transition at the output of the stage of the same transition type. Each stage of the oscillator device also includes a reset module that causes the output signal to be reset to a nominal state a predetermined period of time after the signal transition of the output signal. Each stage thus provides an output signal pulse in response to the signal transition of the designated type at the input. The output of the final stage of the oscillator device is connected to the input, so that the oscillator output provides an oscillating signal having a period based upon the delay path of each the oscillator device stages.Type: GrantFiled: October 23, 2008Date of Patent: January 11, 2011Assignee: Advanced Micro Devices, Inc.Inventors: Arshad I. Nissar, Jan-Michael Huber, Brian M. Lay, Kshitij Seth, Keith Burwinkel, Robert J. Dupcak
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Publication number: 20100102891Abstract: An oscillator device includes a plurality of stages. Each stage is a monostable stage having a delay path, whereby a signal transition of a designated type (rising or falling) at the input of the delay path results in a signal transition at the output of the stage of the same transition type. Each stage of the oscillator device also includes a reset module that causes the output signal to be reset to a nominal state a predetermined period of time after the signal transition of the output signal. Each stage thus provides an output signal pulse in response to the signal transition of the designated type at the input. The output of the final stage of the oscillator device is connected to the input, so that the oscillator output provides an oscillating signal having a period based upon the delay path of each the oscillator device stages.Type: ApplicationFiled: October 23, 2008Publication date: April 29, 2010Applicant: ADVANCED MICRO DEVICES, INC.Inventors: Arshad I. Nissar, Jan-Michael Huber, Brian M. Lay, Kshitij Seth, Keith Burwinkel, Robert J. Dupcak
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Patent number: 6779012Abstract: Computer method and apparatus for performing a square root or division operation generating a root or quotient. A partial remainder is stored in radix-2 or radix-4 signed digit format. A decoder is provided for computing a root or quotient digit, and a correction term dependent on a number of the most significant digits of the partial remainder. An adder is provided for computing the sum of the signed digit partial remainder and the correction term in binary format, and providing the result in signed digit format. The adder computes a carry out independent of a carry in bit and a sum dependent on a Carry_in bit providing a fast adder independent of carry propagate delays. The scaler performs a multiplication by two of the result output from the adder in signed digit format to provide a signed digit next partial remainder.Type: GrantFiled: April 18, 2003Date of Patent: August 17, 2004Assignee: Hewlett-Packard Development Company, L.P.Inventors: Mark D. Matson, Robert J. Dupcak, Jonathan D. Krause, Sridhar Samudrala
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Patent number: 6653869Abstract: A sense amplifier is provided for sensing an input voltage level of a data signal. Such a sense amplifier pre-charges, and subsequently discharges, a pair of nodes through a respective pair of discharge paths. Each of those discharge paths is capable of performing the discharge operation at a rate that is related to either a system voltage supply or an input logic level of the data signal. Because the discharge path that is associated with the data signal includes a greater amount of conductance, it can perform the discharge operation at a faster rate, even where the input logic level does not exceed the voltage of the system voltage supply. A determination is made as to which of the discharge is the faster and, responsively, a rail-to-rail output signal having the same polarity as the data signal, is generated. The input data signal is conveyed to the sense amplifier by a single wire. Also, the sense amplifier does not require a specialized reference voltage for proper operation.Type: GrantFiled: February 15, 2002Date of Patent: November 25, 2003Assignee: Hewlett-Packard Development Company, L.P.Inventors: Robert J. Dupcak, Randy L. Allmon, Mark D. Matson
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Publication number: 20030191786Abstract: Computer method and apparatus for performing a square root or division operation generating a root or quotient. A partial remainder is stored in radix-2 or radix-4 signed digit format. A decoder is provided for computing a root or quotient digit, and a correction term dependent on a number of the most significant digits of the partial remainder. An adder is provided for computing the sum of the signed digit partial remainder and the correction term in binary format, and providing the result in signed digit format. The adder computes a carry out independent of a carry in bit and a sum dependent on a Carry_in bit providing a fast adder independent of carry propagate delays. The scaler performs a multiplication by two of the result output from the adder in signed digit format to provide a signed digit next partial remainder.Type: ApplicationFiled: April 18, 2003Publication date: October 9, 2003Inventors: Mark D. Matson, Robert J. Dupcak, Jonathan D. Krause, Sridhar Samudrala
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Patent number: 6564239Abstract: Computer method and apparatus for performing a square root or division operation generating a root or quotient is presented. A partial remainder is stored in radix-2 or radix-4 signed digit format. A decoder is provided for computing a root or quotient digit, and a correction term dependent on a number of the most significant digits of the partial remainder. An adder is provided for computing the sum of the signed digit partial remainder and the correction term in binary format, and providing the result in signed digit format. The adder computes a carry out independent of a carry in bit and a sum dependent on a Carry_in bit providing a fast adder independent of carry propagate delays. The scaler performs a multiplication by two of the result output from the adder in signed digit format to provide a signed digit next partial remainder.Type: GrantFiled: December 14, 2001Date of Patent: May 13, 2003Assignee: Hewlett-Packard Development Company L.P.Inventors: Mark D. Matson, Robert J. Dupcak, Jonathan D. Krause, Sridhar Samudrala
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Publication number: 20020143839Abstract: The invention provides computer apparatus for performing a square root or division operation generating a root or quotient. A partial remainder is stored in radix-2 or radix-4 signed digit format. A decoder is provided for computing a root or quotient digit, and a correction term dependent on a number of the most significant digits of the partial remainder. An adder is provided for computing the sum of the signed digit partial remainder and the correction term in binary format, and providing the result in signed digit format. The adder computes a carry out independent of a carry in bit and a sum dependent on a Carry_in bit providing a fast adder independent of carry propagate delays. The scaler performs a multiplication by two of the result output from the adder in signed digit format to provide a signed digit next partial remainder.Type: ApplicationFiled: December 14, 2001Publication date: October 3, 2002Applicant: Compaq Computer CorporationInventors: Mark D. Matson, Robert J. Dupcak, Jonathan D. Krause, Sridhar Samudrala
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Publication number: 20020125916Abstract: A sense amplifier is provided for sensing an input voltage level of a data signal. Such a sense amplifier pre-charges, and subsequently discharges, a pair of nodes through a respective pair of discharge paths. Each of those discharge paths is capable of performing the discharge operation at a rate that is related to either a system voltage supply or an input logic level of the data signal. Because the discharge path that is associated with the data signal includes a greater amount of conductance, it can perform the discharge operation at a faster rate, even where the input logic level does not exceed the voltage of the system voltage supply. A determination is made as to which of the discharge is the faster and, responsively, a rail-to-rail output signal having the same polarity as the data signal, is generated. The input data signal is conveyed to the sense amplifier by a single wire. Also, the sense amplifier does not require a specialized reference voltage for proper operation.Type: ApplicationFiled: February 15, 2002Publication date: September 12, 2002Applicant: Compaq Information Technologies Group, L.P.Inventors: Robert J. Dupcak, Randy L. Allmon, Mark D. Matson
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Patent number: 6414520Abstract: A sense amplifier for sensing an input voltage level of a data signal. Such a sense amplifier pre-charges, and subsequently discharges, a pair of nodes through a respective pair of discharge paths. Each of those discharge paths is capable of performing the discharge operation at a rate that is related to either a system voltage supply or an input logic level of the data signal. Because the discharge path that is associated with the data signal includes a greater amount of conductance, it can perform the discharge operation at a faster rate, even where the input logic level does not exceed the voltage of the system voltage supply. A determination is made as to which of the discharge is the faster and, responsively, a rail-to-rail output signal having the same polarity as the data signal, is generated.Type: GrantFiled: February 1, 1999Date of Patent: July 2, 2002Assignee: Compaq Information Technologies Group, L.P.Inventors: Robert J. Dupcak, Randy L. Allmon, Mark D. Matson
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Patent number: 6360241Abstract: The invention provides computer apparatus for performing a square root or division operation generating a root or quotient. A partial remainder is stored in radix-2 or radix-4 signed digit format. A decoder is provided for computing a root or quotient digit, and a correction term dependent on a number of the most significant digits of the partial remainder. An adder is provided for computing the sum of the signed digit partial remainder and the correction term in binary format, and providing the result in signed digit format. The adder computes a carry out independent of a carry in bit and a sum dependent on a Carry_in bit providing a fast adder independent of carry propagate delays. The scaler performs a multiplication by two of the result output from the adder in signed digit format to provide a signed digit next partial remainder.Type: GrantFiled: April 20, 1999Date of Patent: March 19, 2002Assignee: Compaq Information Technologies Goup, L.P.Inventors: Mark D. Matson, Robert J. Dupcak, Jonathan D. Krause, Sridhar Samudrala
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Patent number: 6144228Abstract: A method and apparatus are presented for efficient implementation of logic and arithmetic functions that generate sets of mutually exclusive output signals. Such a logic family includes a network of NMOS transistors that implements a desired logic function. Coupled to that network is a minimal number of PMOS devices for providing logic level restoration and for compensating for any voltage drops due to the NMOS transistors. With such a structure, the speed, area and power consumption characteristics of logic functions are improved.Type: GrantFiled: June 28, 1999Date of Patent: November 7, 2000Assignee: Compaq Computer CorporationInventors: Mark D. Matson, Sridhar Samudrala, Robert J. Dupcak