Patents by Inventor Robert J. Finch

Robert J. Finch has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Stress testing of silicon-on-insulator substrates using applied electrostatic discharge
    Patent number: 8659300
    Abstract: A method of implementing electrostatic discharge (ESD) testing of an integrated circuit includes applying an ESD event to an exposed backside of a substrate of the integrated circuit, wherein the backside of the substrate is electrically isolated from circuit structures formed at a front-end-of-line (FEOL) region of the integrated circuit. The operation of the circuit structures is tested to determine whether the ESD event has caused damage to one or more of the circuit structures as a result of a breakdown in the electrical isolation between the circuit structures and the backside of the substrate.
    Type: Grant
    Filed: December 15, 2010
    Date of Patent: February 25, 2014
    Assignee: International Business Machines Corporation
    Inventors: Robert J. Finch, George A. May
  • STRESS TESTING OF SILICON-ON-INSULATOR SUBSTRATES USING APPLIED ELECTROSTATIC DISCHARGE
    Publication number: 20120153962
    Abstract: A method of implementing electrostatic discharge (ESD) testing of an integrated circuit includes applying an ESD event to an exposed backside of a substrate of the integrated circuit, wherein the backside of the substrate is electrically isolated from circuit structures formed at a front-end-of-line (FEOL) region of the integrated circuit. The operation of the circuit structures is tested to determine whether the ESD event has caused damage to one or more of the circuit structures as a result of a breakdown in the electrical isolation between the circuit structures and the backside of the substrate.
    Type: Application
    Filed: December 15, 2010
    Publication date: June 21, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Robert J. Finch, George A. May
  • ROM storage cell and method of fabrication
    Patent number: 5905670
    Abstract: A process and structure are disclosed for a programmable array for use in a read-only memory comprising diode elements and shorted diode elements. The elements are connected across bit and wordlines. The invention utilizes lateral polysilicon diodes and metal silicide layer bridging the junction of pre-selected diodes to short pre-selected diode elements. Programming is accomplished by either forming the silicide layer across the junctions of pre-selected diodes or removing the silicide layer from the junctions of pre-selected diodes.
    Type: Grant
    Filed: May 13, 1997
    Date of Patent: May 18, 1999
    Assignee: International Business Machines Corp.
    Inventors: Gordon M. Babson, Allen W. Brouillette, Richard J. Evans, Robert J. Finch, Philip H. Noel, Richard J. Ross
  • ROM storage cell and method of fabrication
    Patent number: 5847988
    Abstract: A process and structure are disclosed for a programmable array for use in a read-only memory comprising diode elements and shorted diode elements. The elements are connected across bit and wordlines. The invention utilizes lateral polysilicon diodes and metal silicide layer bridging the junction of pre-selected diodes to short pre-selected diode elements. Programming is accomplished by either forming the silicide layer across the junctions of pre-selected diodes or removing the silicide layer from the junctions of pre-selected diodes.
    Type: Grant
    Filed: January 13, 1998
    Date of Patent: December 8, 1998
    Assignee: International Business Machines Corporation
    Inventors: Gordon M. Babson, Allen W. Brouillette, Richard J. Evans, Robert J. Finch, Philip H. Noel, Richard J. Ross