Patents by Inventor Robert J. Fox

Robert J. Fox has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240152700
    Abstract: List-based entity name detection implementations are described that detect entity names in electronic textural documents. In one implementation, unknown entity names are detected. In another implementation, ambiguous entity names are detected and disambiguated. In yet another implementation, generic entity names are detected and associated with an applicable species entity name.
    Type: Application
    Filed: December 12, 2023
    Publication date: May 9, 2024
    Inventor: Robert J. Fox
  • Publication number: 20240119482
    Abstract: Job profile data analysis implementations that are described herein generally analyzes job profile data, and in various implementations uses the analysis to identify marketing and sales opportunities and threats. More particularly, the job profile data is used to identify individuals who have recently changed jobs and have taken on a decision maker or influencer role in their new job with regard to the purchase of products and/or services. Marketing and sales opportunities and threats are gleaned from this knowledge and the knowledge of what products and services were used in the individual's previous and new jobs.
    Type: Application
    Filed: November 30, 2023
    Publication date: April 11, 2024
    Inventors: Robert J. Fox, Lauren Wong
  • Publication number: 20240086945
    Abstract: Entity functional area and product use identification implementations are described that identify functional areas of an entity and products used by these functional areas. In general, this involves generating a functional area classifier to identify one or more functional areas of the entity inferred in a document, identifying one or more product names found in the document, identifying an entity name in the document (if not already known), and establishing at least one combination of the entity name, the functional area, and a product name for each product name found in the document. In some implementations, at least one of the entity location or the vendor of the named product or the technology designation of the product, is identified in the document and included in the combinations. Multiple documents are processed, and the resulting established combinations are output.
    Type: Application
    Filed: November 15, 2023
    Publication date: March 14, 2024
    Inventors: Robert J. Fox, Abhinav Kaitha
  • Publication number: 20240062229
    Abstract: The probability that an entity will purchase a product is predicted. This prediction involves receiving input data in the form of entries each of which represents an interest event. Through a series of iterations, a final matrix is generated from the input data entries by assigning an entity-product identifier pair associated with each interest event to a different location in the matrix, along with a time identifier indicative of how far back in time the interest event occurred from a prescribed date of interest. A supervised machine learning technique is employed to create a final prediction model for each product of interest using the final matrix as input. For each product, its prediction model is applied to the input data to estimate the probability that an entity will purchase the product within a future time period.
    Type: Application
    Filed: October 23, 2023
    Publication date: February 22, 2024
    Inventors: Robert J. Fox, Samuel B. Chapin, Xining Li
  • Patent number: 11829386
    Abstract: Resume data identification implementations are described that identify anonymized resume corpus data pertaining to the same individual. In one implementation, identifying this data in the anonymized resume corpus involves segmenting the corpus into resume snippets and clustering the resume snippets into groups. Within each group the resume snippets potentially pertain to the same individual. In addition, one or more optional filtering operations can be performed to remove snippets from a group that are less likely to be associated with the same person. This filtering is especially useful when the resume corpus is large.
    Type: Grant
    Filed: January 30, 2020
    Date of Patent: November 28, 2023
    Assignee: HG INSIGHTS, INC.
    Inventors: Robert J. Fox, Samuel B. Chapin, Jonathan C. Frey, Christopher R. Fredregill
  • Publication number: 20230376999
    Abstract: Job profile data analysis implementations that are described herein generally analyzes job profile data, and in various implementations uses the analysis to identify marketing and sales opportunities and threats. More particularly, the job profile data is used to identify individuals who have recently changed jobs and have taken on a decision maker or influencer role in their new job with regard to the purchase of products and/or services. Marketing and sales opportunities and threats are gleaned from this knowledge and the knowledge of what products and services were used in the individual's previous and new jobs.
    Type: Application
    Filed: May 18, 2022
    Publication date: November 23, 2023
    Inventors: Robert J. Fox, Lauren Wong
  • Publication number: 20220284452
    Abstract: Entity functional area and product use identification implementations are described that identify functional areas of an entity and products used by these functional areas. In general, this involves generating a functional area classifier to identify one or more functional areas of the entity inferred in a document, identifying one or more product names found in the document, identifying an entity name in the document (if not already known), and establishing at least one combination of the entity name, the functional area, and a product name for each product name found in the document. In some implementations, at least one of the entity location or the vendor of the named product or the technology designation of the product, is identified in the document and included in the combinations. Multiple documents are processed, and the resulting established combinations are output.
    Type: Application
    Filed: March 5, 2021
    Publication date: September 8, 2022
    Inventors: Robert J. Fox, Abhinav Kaitha
  • Publication number: 20210240737
    Abstract: Resume data identification implementations are described that identify anonymized resume corpus data pertaining to the same individual. In one implementation, identifying this data in the anonymized resume corpus involves segmenting the corpus into resume snippets and clustering the resume snippets into groups. Within each group the resume snippets potentially pertain to the same individual. In addition, one or more optional filtering operations can be performed to remove snippets from a group that are less likely to be associated with the same person. This filtering is especially useful when the resume corpus is large.
    Type: Application
    Filed: January 30, 2020
    Publication date: August 5, 2021
    Inventors: Robert J. Fox, Samuel B. Chapin, Jonathan C. Frey, Christopher R. Fredregill
  • Patent number: 11038011
    Abstract: Methods of fabricating a structure for a metal-insulator-metal (MIM) capacitor. Conductive nanofibers are formed on a surface of a conductor layer. Each conductive nanofiber is terminated by an enlarged tip portion opposite the surface of the conductor layer. The enlarged tip portion is removed from each conductive nanofiber. The MIM capacitor may include the conductive nanofibers as portions of an electrode.
    Type: Grant
    Filed: October 29, 2019
    Date of Patent: June 15, 2021
    Assignee: GLOBALFOUNDRIES U.S. INC.
    Inventors: Lili Cheng, Robert J. Fox, III, Luke England
  • Publication number: 20210126086
    Abstract: Methods of fabricating a structure for a metal-insulator-metal (MIM) capacitor. Conductive nanofibers are formed on a surface of a conductor layer. Each conductive nanofiber is terminated by an enlarged tip portion opposite the surface of the conductor layer. The enlarged tip portion is removed from each conductive nanofiber. The MIM capacitor may include the conductive nanofibers as portions of an electrode.
    Type: Application
    Filed: October 29, 2019
    Publication date: April 29, 2021
    Inventors: Lili Cheng, Robert J. Fox, III, Luke England
  • Publication number: 20210064697
    Abstract: List-based entity name detection implementations are described that detect entity names in electronic textural documents. In one implementation, unknown entity names are detected. In another implementation, ambiguous entity names are detected and disambiguated. In yet another implementation, generic entity names are detected and associated with an applicable species entity name.
    Type: Application
    Filed: August 26, 2019
    Publication date: March 4, 2021
    Inventor: Robert J. Fox
  • Publication number: 20200380540
    Abstract: The probability that an entity will purchase a product is predicted. This prediction involves receiving input data in the form of entries each of which represents an interest event. Through a series of iterations, a final matrix is generated from the input data entries by assigning an entity-product identifier pair associated with each interest event to a different location in the matrix, along with a time identifier indicative of how far back in time the interest event occurred from a prescribed date of interest. A supervised machine learning technique is employed to create a final prediction model for each product of interest using the final matrix as input. For each product, its prediction model is applied to the input data to estimate the probability that an entity will purchase the product within a future time period.
    Type: Application
    Filed: May 30, 2019
    Publication date: December 3, 2020
    Inventors: Robert J. Fox, Samuel B. Chapin, Xining Li
  • Patent number: 10580581
    Abstract: Methods for fabricating a structure that includes a metal-insulator-metal (MIM) capacitor and structures that include a MIM capacitor. The MIM capacitor includes a layer stack with a first electrode, a second electrode, and a third electrode. The layer stack includes a pilot opening extending at least partially through at least one of the first electrode, the second electrode, and the third electrode. A dielectric layer is arranged over the metal-insulator-metal capacitor, and includes a via opening extending vertically to the pilot opening. A via is arranged in the via opening and the pilot opening. The pilot opening has a cross-sectional area that is less than a cross-sectional area of the via opening.
    Type: Grant
    Filed: November 16, 2017
    Date of Patent: March 3, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Robert J. Fox, III, Lili Cheng, Roderick A. Augur
  • Publication number: 20190148072
    Abstract: Methods for fabricating a structure that includes a metal-insulator-metal (MIM) capacitor and structures that include a MIM capacitor. The MIM capacitor includes a layer stack with a first electrode, a second electrode, and a third electrode. The layer stack includes a pilot opening extending at least partially through at least one of the first electrode, the second electrode, and the third electrode. A dielectric layer is arranged over the metal-insulator-metal capacitor, and includes a via opening extending vertically to the pilot opening. A via is arranged in the via opening and the pilot opening. The pilot opening has a cross-sectional area that is less than a cross-sectional area of the via opening.
    Type: Application
    Filed: November 16, 2017
    Publication date: May 16, 2019
    Inventors: Robert J. Fox, III, Lili Cheng, Roderick A. Augur
  • Patent number: 10236206
    Abstract: Structures for interconnects and methods for forming interconnects. A dual-damascene opening is formed in a dielectric layer and a first liner is formed on the dielectric layer at one or more sidewalls of the dual-damascene opening. A first conductor layer is formed in a portion of the dual-damascene opening. The first liner is removed from the one or more sidewalls of the dual-damascene opening vertically between the first conductor layer and a top surface of the dielectric layer. After the first liner is removed, a second liner is formed on the dielectric layer at the one or more sidewalls of the dual-damascene opening between the first conductor layer and the top surface of the dielectric layer. A second conductor layer is formed in the dual-damascene opening between the first conductor layer and the top surface of the dielectric layer. The first and second liner materials differ in composition.
    Type: Grant
    Filed: July 3, 2017
    Date of Patent: March 19, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventor: Robert J. Fox, III
  • Patent number: 10177029
    Abstract: Interconnect structures and methods for forming an interconnect structure. A sacrificial layer is formed on a substrate and an interconnect opening is formed that extends vertically through the sacrificial layer into the substrate. The interconnect opening is filled with a conductor to form a conductive feature. After filling the interconnect opening with the conductor, a dielectric layer is formed on the sacrificial layer. After the dielectric layer is formed on the sacrificial layer, the sacrificial layer is removed to form an air gap layer arranged vertically between the dielectric layer and the substrate.
    Type: Grant
    Filed: October 23, 2017
    Date of Patent: January 8, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Robert J. Fox, III, Sunil K. Singh
  • Publication number: 20190006234
    Abstract: Structures for interconnects and methods for forming interconnects. A dual-damascene opening is formed in a dielectric layer and a first liner is formed on the dielectric layer at one or more sidewalls of the dual-damascene opening. A first conductor layer is formed in a portion of the dual-damascene opening. The first liner is removed from the one or more sidewalls of the dual-damascene opening vertically between the first conductor layer and a top surface of the dielectric layer. After the first liner is removed, a second liner is formed on the dielectric layer at the one or more sidewalls of the dual-damascene opening between the first conductor layer and the top surface of the dielectric layer. A second conductor layer is formed in the dual-damascene opening between the first conductor layer and the top surface of the dielectric layer. The first and second liner materials differ in composition.
    Type: Application
    Filed: July 3, 2017
    Publication date: January 3, 2019
    Inventor: Robert J. Fox, III
  • Patent number: 10153232
    Abstract: A crack stop structure for an integrated circuit (IC) structure is disclosed. The structure can include: a first crack stop pillar laterally separated from a second crack stop pillar within an insulator region of the IC structure. The first crack stop pillar can include an overlapping via in contact with a top surface and at least one side surface of a first conductive element therebelow. The overlapping via of the first crack stop pillar may be in a given layer of the IC structure, and the second crack stop pillar may include a via in the given layer, the via extending to a different depth than the overlapping via. The via of the second crack stop pillar may be an overlapping via in contact with a top surface and at least one side surface of a second conductive element therebelow.
    Type: Grant
    Filed: April 26, 2017
    Date of Patent: December 11, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Robert J. Fox, III, Kevin M. Boyd, Nicholas A. Polomoff, Roderick A. Augur, Jeannine M. Trewhella
  • Publication number: 20180315707
    Abstract: A crack stop structure for an integrated circuit (IC) structure is disclosed. The structure can include: a first crack stop pillar laterally separated from a second crack stop pillar within an insulator region of the IC structure. The first crack stop pillar can include an overlapping via in contact with a top surface and at least one side surface of a first conductive element therebelow. The overlapping via of the first crack stop pillar may be in a given layer of the IC structure, and the second crack stop pillar may include a via in the given layer, the via extending to a different depth than the overlapping via. The via of the second crack stop pillar may be an overlapping via in contact with a top surface and at least one side surface of a second conductive element therebelow.
    Type: Application
    Filed: April 26, 2017
    Publication date: November 1, 2018
    Inventors: Robert J. Fox, III, Kevin M. Boyd, Nicholas A. Polomoff, Roderick A. Augur, Jeannine M. Trewhella
  • Patent number: D1022120
    Type: Grant
    Filed: October 21, 2021
    Date of Patent: April 9, 2024
    Inventor: Robert J. Fox