Abstract: A multi-module, multi-port memory system includes modules having semiconductor memory circuits which require periodic refreshing to retain the contents stored therein. Priority circuits resolve conflicts between the multi-port access of the memory modules and the refreshing requirements of semiconductor memory circuits within the modules. The modules of the preferred embodiment are arranged in a polymorphous array of selectably expendable rows and columns. Modules utilizing different memory technologies may be combined within the address space of the array without interfering with independent multi-port access by various computer processors and other memory using devices.