Abstract: In a switched-mode power supply, when the controller and the switching device are encapsulated together with a heat sink, in which the drain of the switching device is connected to the heat sink, the heat sink and the paths to the various pins of the controller forms various parasitic capacitances which, when the switching device switches, injects and withdraws inordinately large currents into and from the pins of the controller. In the case of the V.sub.CTRL pin to which is connected a discharge capacitor, the resulting under voltage across the capacitor may be used by circuitry connected to the V.sub.CTRL pin to control the switching of the switching device resulting in throwing the switched-mode power supply out of regulation. A track-and-hold circuit is now connected between the V.sub.CTRL pin and the circuitry to mirror the voltage across the discharge capacitor.

Abstract: Picture display device with one or more resonant selection pulse drivers for generating selection pulses for selecting rows of pixels. The resonant selection pulse driver has two driver output electrodes to which selection electrode(s) are connected for simultaneously generating a pulse trailing edge at one driver output electrode and generating a pulse leading edge at the other driver output electrode.

Abstract: A level-shifting circuit (LS.sub.A) including a series arrangement of a load resistor (R.sub.A), a main current path of an input transistor and a bipolar series transistor (T3.sub.A) arranged as a current source and having a parasitic transistor with a small current gain factor, which is obtained, for example, by wholly surrounding the comparatively weakly doped collector region with a comparatively heavily doped material of the same conductivity type as the collector region. When the input transistor (T1.sub.A) is not conductive a large amount of charge accumulates in the series transistor (T3.sub.A), which is then in saturation. When the input transistor (T1.sub.A) is turned on the accumulated charge causes an overshoot in the current (I.sub.A) through the level-shifter which overshoot compensates for the slow response as a result of the parasitic capacitance (PC.sub.A) at the node (N.sub.A).

Abstract: A motor control arrangement including a control circuit for controlling the speed of an electric motor (EM), which control circuit comprises a measurement resistor (MR) and a switching transistor (ST) having a control electrode and a main current path coupled in series with the electric motor (EM) and the measurement resistor (MR), a pulse width control stage (PW) coupled to the control electrode of the switching transistor (ST), a motor current measurement stage (MI) for controlling the pulse width control stage (PW) in response to a motor current of the electric motor (EM), and a motor voltage measurement stage (MV) for controlling the pulse width control stage (PW) in response to a motor voltage (EM) of the electric motor (EM).

Abstract: A reference current source for generating a reference current (Irf) includes a bipolar first transistor (2) and a bipolar second transistor (4), the base of the first transistor (2) being coupled to the base of the second transistor (4), a first resistor (6) connected between the emitter of the first transistor (2) and the emitter of the second transistor (4), and a second resistor (8) connected between the emitter of the second transistor (4) and a supply terminal (10).