Abstract: The present disclosure includes apparatuses, methods, and systems for error detection and correction in memory. An embodiment includes a memory having a group of self-selecting memory cells which store data corresponding to a codeword from an error correcting code, and circuitry configured to perform a sense operation on the group of self-selecting memory cells, identify, based on the sense operation, memory cells of the group that cannot store data, mark data sensed from the identified memory cells as erasures and perform an error correction operation on data sensed from the group of self-selecting memory cells with the data sensed from the identified memory cells marked as erasures.

Abstract: The present disclosure includes apparatuses, methods, and systems for predicting and compensating for degradation of memory cells. An embodiment includes a memory having a group of memory cells, and circuitry configured to, upon a quantity of sense operations performed on the group of memory cells meeting or exceeding a threshold quantity, perform a sense operation on the group of memory cells using a positive sensing voltage and perform a sense operation on the group of memory cells using a negative sensing voltage, and perform an operation to program the memory cells of the group determined to be in a reset data state by both of the sense operations to the reset data state.

Abstract: Apparatuses, methods, and systems for generating patterns for memory using threshold voltage difference are disclosed. An embodiment includes circuitry and a memory array including a plurality of memory cells. The circuitry can select a group of memory cells from the plurality of memory cells, program each memory cell of the group to a first data state, determine a first threshold voltage of each memory cell of the group, program each memory cell of the group to a second data state, perform a number of snapback events on each memory cell of the group, program each memory cell of the group to the first data state, determine a second threshold voltage of each memory cell of the group having the first data state, and generate a pattern for the memory array based, at least in part, on a difference between the first threshold voltage and the second threshold voltage.

Abstract: The present disclosure includes apparatuses, methods, and systems for increase of a sense current in memory. An embodiment includes a memory having a plurality of memory cells, and circuitry configured to apply, prior to sensing a data state of a memory cell of the plurality of memory cells, a voltage to an access line to which the memory cell is coupled, determine whether an amount of current on the access line in response to the applied voltage meets or exceeds a threshold amount of current, and determine whether to increase a magnitude of a current used to sense the data state of the memory cell based on whether the amount of current on the access line in response to the applied voltage meets or exceeds the threshold amount of current.

Abstract: The present disclosure includes apparatuses and methods related to forming memory cells having memory element dimensions. For example, a memory cell may include a first electrode, a select-element material between the first electrode and a second electrode, and a lamina between the select-element material and the first electrode. The first electrode may comprise a first portion, proximate to the lamina, having a first lateral dimension; and a second portion, distal from the lamina, having a second lateral dimension, wherein the second lateral dimension is greater than the first lateral dimension.

Abstract: Methods, systems, and devices for write operation techniques for memory systems are described. In some memory systems, write operations performed on target memory cells of the memory device may disturb logic states stored by one or more adjacent memory cells. Such disturbances may cause reductions in read margins when accessing one or more memory cells, or may cause a loss of data in one or more memory cells. The described techniques may reduce aspects of logic state degradation by supporting operational modes where a host device, a memory device, or both, refrains from writing information to a region of a memory array, or inhibits write commands associated with write operations on a region of a memory array.

Abstract: The present disclosure includes apparatuses, methods, and systems for increase of a sense current in memory. An embodiment includes a memory having a plurality of memory cells, and circuitry configured to count a number of program operations performed on the memory cells of the memory during operation of the memory, and increase a magnitude of a current used to sense a data state of the memory cells of the memory upon the count of the number of program operations reaching a threshold count.

Abstract: The present disclosure includes systems, apparatuses, and methods related to generating a random data value. For example, a first read operation may be performed on a memory cell programmed to a first state, wherein the first read operation is performed using a first read voltage that is within a predetermined threshold voltage distribution corresponding to the first state. A programming signal may be applied to the memory cell responsive to the first read operation resulting in a snapback event, wherein the programming signal is configured to place the memory cell in a second state. A second read operation may be performed to determine whether the memory cell is in the first state or the second state using a second read voltage that is between the predetermined threshold voltage distribution corresponding to the first state and a second threshold voltage distribution corresponding to the second state.

Abstract: Methods and systems include memory devices with multiple memory cells configured to store data. The memory devices also include a cache configured to store at least a portion of the data to provide access to the at least the portion of the data without accessing the multiple memory cells. The memory devices also include control circuitry configured to receive a read command having a target address. Based on the target address, the control circuitry is configured to determine that the at least the portion of the data is present in the cache. Using the cache, the control circuitry also outputs read data from the cache without accessing the plurality of memory cells.

Abstract: The present disclosure includes apparatuses, methods, and systems for predicting and compensating for degradation of memory cells. An embodiment includes a memory having a group of memory cells, and circuitry configured to, upon a quantity of sense operations performed on the group of memory cells meeting or exceeding a threshold quantity, perform a sense operation on the group of memory cells using a positive sensing voltage and perform a sense operation on the group of memory cells using a negative sensing voltage, and perform an operation to program the memory cells of the group determined to be in a reset data state by both of the sense operations to the reset data state.

Abstract: The present disclosure includes apparatuses, methods, and systems for error detection and correction in memory. An embodiment includes a memory having a group of self-selecting memory cells which store data corresponding to a codeword from an error correcting code, and circuitry configured to perform a sense operation on the group of self-selecting memory cells, identify, based on the sense operation, memory cells of the group that cannot store data, mark data sensed from the identified memory cells as erasures and perform an error correction operation on data sensed from the group of self-selecting memory cells with the data sensed from the identified memory cells marked as erasures.

Abstract: The present disclosure includes systems, apparatuses, and methods related to generating a random data value. For example, a first read operation may be performed on a memory cell programmed to a first state, wherein the first read operation is performed using a first read voltage that is within a predetermined threshold voltage distribution corresponding to the first state. A programming signal may be applied to the memory cell responsive to the first read operation resulting in a snapback event, wherein the programming signal is configured to place the memory cell in a second state. A second read operation may be performed to determine whether the memory cell is in the first state or the second state using a second read voltage that is between the predetermined threshold voltage distribution corresponding to the first state and a second threshold voltage distribution corresponding to the second state.

Abstract: The present disclosure includes apparatuses, methods, and systems for predicting and compensating for degradation of memory cells. An embodiment includes a memory having a group of memory cells, and circuitry configured to, upon a quantity of sense operations performed on the group of memory cells meeting or exceeding a threshold quantity, perform a sense operation on the group of memory cells using a positive sensing voltage and perform a sense operation on the group of memory cells using a negative sensing voltage, and perform an operation to program the memory cells of the group determined to be in a reset data state by both of the sense operations to the reset data state.

Abstract: The present disclosure includes apparatuses, methods, and systems for error detection and correction in memory. An embodiment includes a memory having a group of self-selecting memory cells which store data corresponding to a codeword from an error correcting code, and circuitry configured to perform a sense operation on the group of self-selecting memory cells, identify, based on the sense operation, memory cells of the group that cannot store data, mark data sensed from the identified memory cells as erasures and perform an error correction operation on data sensed from the group of self-selecting memory cells with the data sensed from the identified memory cells marked as erasures.

Abstract: The present disclosure includes apparatuses, methods, and systems for predicting and compensating for degradation of memory cells. An embodiment includes a memory having a group of memory cells, and circuitry configured to, upon a quantity of sense operations performed on the group of memory cells meeting or exceeding a threshold quantity, perform a sense operation on the group of memory cells using a positive sensing voltage and perform a sense operation on the group of memory cells using a negative sensing voltage, and perform an operation to program the memory cells of the group determined to be in a reset data state by both of the sense operations to the reset data state.

Abstract: Methods and systems include memory devices with multiple memory cells configured to store data. The memory devices also include a cache configured to store at least a portion of the data to provide access to the at least the portion of the data without accessing the multiple memory cells. The memory devices also include control circuitry configured to receive a read command having a target address. Based on the target address, the control circuitry is configured to determine that the at least the portion of the data is present in the cache. Using the cache, the control circuitry also outputs read data from the cache without accessing the plurality of memory cells.

Abstract: The present disclosure includes apparatuses, methods, and systems for increase of a sense current in memory. An embodiment includes a memory having a plurality of memory cells, and circuitry configured to apply, prior to sensing a data state of a memory cell of the plurality of memory cells, a voltage to an access line to which the memory cell is coupled, determine whether an amount of current on the access line in response to the applied voltage meets or exceeds a threshold amount of current, and determine whether to increase a magnitude of a current used to sense the data state of the memory cell based on whether the amount of current on the access line in response to the applied voltage meets or exceeds the threshold amount of current.

Abstract: Methods, systems, and devices for write operation techniques for memory systems are described. In some memory systems, write operations performed on target memory cells of the memory device may disturb logic states stored by one or more adjacent memory cells. Such disturbances may cause reductions in read margins when accessing one or more memory cells, or may cause a loss of data in one or more memory cells. The described techniques may reduce aspects of logic state degradation by supporting operational modes where a host device, a memory device, or both, refrains from writing information to a region of a memory array, or inhibits write commands associated with write operations on a region of a memory array.

Abstract: The present disclosure includes apparatuses, methods, and systems for increase of a sense current in memory. An embodiment includes a memory having a plurality of memory cells, and circuitry configured to count a number of program operations performed on the memory cells of the memory during operation of the memory, and increase a magnitude of a current used to sense a data state of the memory cells of the memory upon the count of the number of program operations reaching a threshold count.

Abstract: The present disclosure includes apparatuses, methods, and systems for increase of a sense current in memory. An embodiment includes a memory having a plurality of memory cells, and circuitry configured to apply, prior to sensing a data state of a memory cell of the plurality of memory cells, a voltage to an access line to which the memory cell is coupled, determine whether an amount of current on the access line in response to the applied voltage meets or exceeds a threshold amount of current, and determine whether to increase a magnitude of a current used to sense the data state of the memory cell based on whether the amount of current on the access line in response to the applied voltage meets or exceeds the threshold amount of current.