Patents by Inventor Robert J. Halstead

Robert J. Halstead has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Data filtering using a plurality of hardware accelerators
    Patent number: 11615069
    Abstract: Techniques are provided for data filtering using hardware accelerators. An apparatus comprises a processor, a memory and a plurality of hardware accelerators. The processor is configured to stream data from the memory to a first one of the hardware accelerators and to receive filtered data from a second one of the hardware accelerators. The plurality of hardware accelerators are configured to filter the streamed data utilizing at least one bit vector partitioned across the plurality of hardware accelerators. The hardware accelerators may be field-programmable gate arrays.
    Type: Grant
    Filed: May 15, 2019
    Date of Patent: March 28, 2023
    Assignee: International Business Machines Corporation
    Inventors: Sameh W. Asaad, Robert J. Halstead, Bharat Sukhwani
  • DATA FILTERING USING A PLURALITY OF HARDWARE ACCELERATORS
    Publication number: 20190266149
    Abstract: Techniques are provided for data filtering using hardware accelerators. An apparatus comprises a processor, a memory and a plurality of hardware accelerators. The processor is configured to stream data from the memory to a first one of the hardware accelerators and to receive filtered data from a second one of the hardware accelerators. The plurality of hardware accelerators are configured to filter the streamed data utilizing at least one bit vector partitioned across the plurality of hardware accelerators. The hardware accelerators may be field-programmable gate arrays.
    Type: Application
    Filed: May 15, 2019
    Publication date: August 29, 2019
    Inventors: Sameh Asaad, Robert J. Halstead, Bharat Sukhwani
  • Data filtering using a plurality of hardware accelerators
    Patent number: 10387403
    Abstract: Techniques are provided for data filtering using hardware accelerators. An apparatus comprises a processor, a memory and a plurality of hardware accelerators. The processor is configured to stream data from the memory to a first one of the hardware accelerators and to receive filtered data from a second one of the hardware accelerators. The plurality of hardware accelerators are configured to filter the streamed data utilizing at least one bit vector partitioned across the plurality of hardware accelerators. The hardware accelerators may be field-programmable gate arrays.
    Type: Grant
    Filed: July 6, 2015
    Date of Patent: August 20, 2019
    Assignee: International Business Machines Corporation
    Inventors: Sameh W. Asaad, Robert J. Halstead, Bharat Sukhwani
  • Data filtering using a plurality of hardware accelerators
    Patent number: 10372700
    Abstract: Techniques are provided for data filtering using hardware accelerators. An apparatus comprises a processor, a memory and a plurality of hardware accelerators. The processor is configured to stream data from the memory to a first one of the hardware accelerators and to receive filtered data from a second one of the hardware accelerators. The plurality of hardware accelerators are configured to filter the streamed data utilizing at least one bit vector partitioned across the plurality of hardware accelerators. The hardware accelerators may be field-programmable gate arrays.
    Type: Grant
    Filed: March 30, 2015
    Date of Patent: August 6, 2019
    Assignee: International Business Machines Corporation
    Inventors: Sameh W. Asaad, Robert J. Halstead, Bharat Sukhwani
  • DATA FILTERING USING A PLURALITY OF HARDWARE ACCELERATORS
    Publication number: 20160292209
    Abstract: Techniques are provided for data filtering using hardware accelerators. An apparatus comprises a processor, a memory and a plurality of hardware accelerators. The processor is configured to stream data from the memory to a first one of the hardware accelerators and to receive filtered data from a second one of the hardware accelerators. The plurality of hardware accelerators are configured to filter the streamed data utilizing at least one bit vector partitioned across the plurality of hardware accelerators. The hardware accelerators may be field-programmable gate arrays.
    Type: Application
    Filed: July 6, 2015
    Publication date: October 6, 2016
    Inventors: Sameh W. Asaad, Robert J. Halstead, Bharat Sukhwani
  • DATA FILTERING USING A PLURALITY OF HARDWARE ACCELERATORS
    Publication number: 20160292201
    Abstract: Techniques are provided for data filtering using hardware accelerators. An apparatus comprises a processor, a memory and a plurality of hardware accelerators. The processor is configured to stream data from the memory to a first one of the hardware accelerators and to receive filtered data from a second one of the hardware accelerators. The plurality of hardware accelerators are configured to filter the streamed data utilizing at least one bit vector partitioned across the plurality of hardware accelerators. The hardware accelerators may be field-programmable gate arrays.
    Type: Application
    Filed: March 30, 2015
    Publication date: October 6, 2016
    Inventors: Sameh W. Asaad, Robert J. Halstead, Bharat Sukhwani