Abstract: A power monitor for electronic devices, such as computer chips, is used to estimate the power consumption and to compare the estimated power consumption against the power budget. The estimated power consumption is based on activity signals from various functional blocks of the computer chip. The activity signals that are monitored correlate accurately to the total number of flip-flops that are active at a given time. If the estimated power consumption exceeds the power budget, the speed of the clock signals supplied to the computer chip is reduced.

Abstract: An embodiment of the invention includes receiving an indicator of an activity-level of a functional block within an electronic chip. The functional block is configured to receive a clock signal from a clock signal generator. The clock signal to at least a portion of a functional block is disabled for a number of inactive clock cycles during a clock segment of the clock signal. The clock segment has a specified number of clock cycles and the number of inactive clock cycles is defined based on the activity-level and the specified number of clock cycles of the clock segment.

Abstract: An embodiment of the invention includes receiving an indicator of a flow of data associated with a graphics processing stage within a graphics pipeline of a graphics processor. A clock signal to a portion of the graphics processing stage is modified based on a status of the flow of data. The clock signal is received from a clock signal generator within the graphics processor.

Abstract: An embodiment of the invention includes receiving an indicator of an activity-level of a functional block within an electronic chip. The functional block is included in a processing pipeline having a plurality of functional blocks. Each functional block from the plurality is configured to receive a clock signal from a clock signal generator. A status of the functional block is determined based on the activity-level. The clock signal to at least a portion of the functional block is disabled when the status is an inactive status.

Abstract: A prototype development apparatus includes a logic board (LB) including a plurality of integrated circuit (IC) sites each adapted to receive an IC, logic traces coupled to each of the IC sites, and a plurality of logic board connector sites (LBCSs) configured to provide access to a number of the logic traces and each adapted to receive a connector. Additionally, a mezzanine board (MB) has a plurality of mezzanine board connector sites (MBCSs) each adapted to receive a connector and configured to provide access to a number of mezzanine traces interconnecting the LBCSs. The MB board is coupled to the LB and a portion of the logic traces are coupled to a portion of the mezzanine traces. In another embodiment the MB does not have any active components. This is because in this embodiment, the MB is configured to connect the pins of the connector sites according to a predetermined program.

Abstract: A prototype development apparatus includes a logic board (LB) including a plurality of integrated circuit (IC) sites each adapted to receive an IC, logic traces coupled to each of the IC sites, and a plurality of logic board connector sites (LBCSs) configured to provide access to a number of the logic traces and each adapted to receive a connector. Additionally, a mezzanine board (MB) has a plurality of mezzanine board connector sites (MBCSs) each adapted to receive a connector and configured to provide access to a number of mezzanine traces interconnecting the LBCSs. The MB board is coupled to the LB and a portion of the logic traces are coupled to a portion of the mezzanine traces. In another embodiment the MB does not have any active components. This is because in this embodiment, the MB is configured to connect the pins of the connector sites according to a predetermined program.