Abstract: In a method of testing a semiconductor wafer or sample having a dielectric layer overlaying a substrate of semiconducting material, a contact is caused to touch a top surface of the dielectric layer. At least a portion of the contact touching the dielectric layer is formed of iridium. A controlled electrical stimulus that causes the dielectric layer to breakdown and an electrically conductive path to form through the dielectric layer is applied to the contact touching the top surface of the dielectric layer. Either a value of the controlled electrical stimulus where breakdown of the dielectric layer occurs or a time for the breakdown of the dielectric layer to occur in response to the application of the controlled electrical stimulus is determined. From the thus determined value or time, a determination can be made whether the dielectric layer is within acceptable tolerance.

Abstract: A semiconductor wafer or sample having a substrate of semiconducting material is tested by compressing a dielectric between three electrically conductive contacts and a top surface of the semiconductor wafer or sample substrate. The dielectric has a thickness that permits tunneling current to flow therethrough without damaging the dielectric. A first electrical bias is applied to a pair of adjacent contacts and a second electrical bias, such as ground reference, is applied to the other contact whereupon an inversion layer forms in the semiconductor wafer or sample. A value of a current that flows in the semiconductor wafer or sample substrate and across the dielectric, in the form of a tunneling current, is measured in response to the applied electrical biases. A surface mobility of minority carriers in the semiconductor wafer or sample is determined as a function of the applied electrical biases and the value of the measured current.

Abstract: In a method and apparatus for determining one or more electrical properties of a semiconductor wafer or sample, the response of a semiconductor wafer or sample to an applied CV-type electrical stimulus is measured. Utilizing a recursive technique, progressively more accurate values of equivalent oxide thickness CET, maximum capacitance Cox, flatband voltage Vfb and other properties of the semiconductor wafer or sample are determined from the measured response. An equivalent oxide thickness EOT of the semiconductor wafer or sample can be determined as a function of the most accurate value of CET determined based upon convergence of at least one of (1) the last two values of Cox or (2) the last two values of Vfb within a predetermined convergence criteria. One or more of the EOT value and/or values of one or more of CET, Cox or Vfb can then be output in a human detectable form.

Abstract: In a method of determining that a semiconductor wafer or sample has a desirable density of electrically active dopant, minimum and maximum capacitances associated with the semiconducting material forming the wafer or sample at a first point adjacent a topside thereof are determined and minimum and maximum capacitances associated with the semiconducting material forming the wafer or sample at a second point adjacent a beveled surface thereof that is defined by the removal of a portion of the topside thereabove are determined. As a function of the minimum and maximum capacitances determined at each point and the depth on or from the topside surface where each point resides, the electrically active dopant density of the semiconductor wafer or sample can be determined.

Abstract: To determine the generation lifetime of a pn junction of a semiconductor wafer, an elastically deformable, electrically conductive contact is caused to touch a surface of the semiconductor wafer over the pn junction. At least one reverse bias voltage is applied to the pn junction via the contact and a value of current flowing in the contact in response to the application of each reverse bias voltage is measured. The generation lifetime of the pn junction is then determined from a subset of the values of the reverse bias voltage and the corresponding values of measured current.

Abstract: In a method of measuring at least one electrical property of a semiconductor wafer, an elastically deformable conductive contact formed from an electrically conductive coating overlaying an electrically conductive base material is provided. The base material has a first work function and the coating has a second work function. A first electrical contact is formed between the conductive contact and a top surface of a semiconductor wafer. A second electrical contact is formed with the semiconductor wafer. An electrical stimulus is applied between the first and second electrical contacts and a response of the semiconductor wafer to the electrical stimulus is measured. At least one electrical property of the semiconductor wafer is determined from the response.

Abstract: To detect soft breakdown of a dielectric layer of a semiconductor wafer, a DC current is caused to flow between a top surface of the dielectric layer and the semiconducting material of the semiconductor wafer. The DC current is either a constant value DC current, or a DC current that swept and/or stepped from a first value toward a second value in a manner whereupon the electric field and, hence, a DC voltage induced across the dielectric layer increases as the DC current approaches the second value. The response of the semiconductor wafer to the flow of DC current is measured for the presence of an AC voltage component superimposed on the DC voltage. The value of the DC voltage induced across the dielectric layer where the AC voltage component is detected is designated as the soft breakdown voltage of the dielectric layer.

Abstract: A method of characterizing a silicon-on-insulator (SOI) wafer, comprised of an insulating layer sandwiched between a semiconductor top layer and a semiconductor substrate, includes moving a pair of spaced conductors into contact with a surface of the wafer exposed on a side thereof opposite the substrate. First and second biases are applied to the substrate and at least one of the conductors. At least one of the first and second biases are swept from a first value toward a second value and the current flowing through the SOI wafer in response to said sweep is measured. At least one characteristic of the wafer is determined from the measured current as a function of the one swept bias.

Abstract: A leakage current of a dielectric overlaying a semiconductor wafer can be determining by moving a conductive probe into contact with the dielectric and applying an electrical stimulus, in the form of a fixed amplitude, fixed frequency AC voltage superimposed on a DC voltage which is swept from a starting voltage towards an ending voltage, between the probe tip and the semiconductor wafer. Conductance values associated with the dielectric and the semiconductor wafer can be determined from phase angles between the AC voltage and an AC current resulting from the applied AC voltage during the sweep of the DC voltage. The leakage current of the dielectric can then be determined from the thus determined conductance values.

Abstract: A product semiconductor wafer has integrated circuits separated by scribe lines. A probe having an elastically de-formable, electrically conductive tip is moved into contact with one of the scribe lines thereby forming a test structure. A suitable electrical stimulus is applied to the test structure and a response of the test structure to the electrical stimulus is measured. At least one property of the product semiconductor wafer is determined from the response.

Abstract: A product semiconductor wafer has integrated circuits separated by scribe lines. A probe having an elastically deformable, electrically conductive tip is moved into contact with one of the scribe lines thereby forming a test structure. A suitable electrical stimulus is applied to the test structure and a response of the test structure to the electrical stimulus is measured. At least one property of the product semiconductor wafer is determined from the response.

Abstract: A semiconductor wafer probe assembly (10) includes a chuck assembly (18, 20) configured to receive a back surface (30) of a semiconductor wafer (14) and an electrical contact (20) for contacting the semiconductor wafer (14). A probe (36) having an elastically deformable conductive tip (38) is movable into contact with a semiconducting material forming a front surface (13) of the semiconductor wafer (14) or with a front surface (34) of a dielectric (12) formed on the front surface of the semiconducting material. A tester (82) is connected for applying an electrical stimulus between the electrical contact (20) and the conductive tip (38) for measuring a response to the electrical stimulus and for determining from the response at least one electrical property of the semiconducting material and/or the dielectric (12).

Abstract: A product semiconductor wafer has integrated circuits separated by scribe lines. A probe having an elastically deformable, electrically conductive tip is moved into contact with one of the scribe lines thereby forming a test structure. A suitable electrical stimulus is applied to the test structure and a response of the test structure to the electrical stimulus is measured. At least one property of the product semiconductor wafer is determined from the response.

Abstract: An apparatus for conducting noncontact capacitance versus voltage measurements over a flat surface of a test wafer comprises a capacitance measuring head mounted on a positioning arm. The positioning arm is kinematically mounted and positions the measuring head over the test wafer. The capacitance measuring head has a plurality of electrically separate capacitor plates, one for use in making the capacitance versus voltage measurements and the remaining plates for providing capacitive position signals. Actuators responsive to the position signals place the measuring head very close to and substantially parallel to the surface of the test wafer.

Abstract: An apparatus and method for measurement of electrical properties of a dielectric layer on a semiconductor wafer body is disclosed. The apparatus supports the semiconductor wafer body in position and two electrical contacts are utilized, one of which is a probe tip having a uniformly flat contact portion. Means are provided for establishing a planar contact between the flat contact portion of the probe tip and the dielectric layer of the semiconductor wafer. Measurements of the electrical properties of the dielectric layer can then be made without the use of patterned mesas.