Abstract: A shared bypass bus structure for low-latency coherency controller access in a coherent scalable switch. In a coherent scalable switch with multiple coherent interconnect ports, distributed coherency control structures, and a crossbar interface between them, a shared bypass bus permits data transfer between the coherent interconnect ports and the coherency control structures while bypassing the crossbar interface. Some embodiments may comprise scalable switches to support one or more sets of processors with substantially independent snoop or cache coherency paths or arrangements.

Abstract: In a multi-node computing system, the originating receiving device receives a broadcast request, decodes the broadcast request, and transmits a broadcast header to a primary tagging device. The primary tagging device generates at least one tagged broadcast header and transmits the at least one tagged broadcast header to the originating receiving device. The originating receiving device transmits tagged broadcast transaction(s) to broadcast receiving device(s). The broadcast receiving device(s) transmits the tagged broadcast transaction(s) to a broadcast node(s). The broadcast node(s) transmits a node completion signal(s) to the broadcast receiving device(s). The broadcast receiving device(s) transmits all of the node completion signal(s) to the primary tagging device. The primary tagging device transmits a transaction completion signal to the originating receiving device.

Abstract: A shared bypass bus structure for low-latency coherency controller access in a coherent scalable switch. In a coherent scalable switch with multiple coherent interconnect ports, distributed coherency control structures, and a crossbar interface between them, a shared bypass bus permits data transfer between the coherent interconnect ports and the coherency control structures while bypassing the crossbar interface. Some embodiments may comprise scalable switches to support one or more sets of processors with substantially independent snoop or cache coherency paths or arrangements.