Patents by Inventor Robert J. Johnsen

Robert J. Johnsen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6900105
    Abstract: In a semiconductor manufacturing method, an emitter region (211) and a base enhancement region (207) are formed to provide linear voltage, capacitance and low resistance characteristics. In the manufacturing method, a semiconductor device (200) is formed on a silicon substrate layer (101) with an epitaxial layer (203). Trenches (233) are cut into the epitaxial layer (203) and filled with oxide (601) to provide reduced junction capacitance and reduced base resistance. The emitter region (211) and the base enhancement region (207) are simultaneously formed through an anneal process.
    Type: Grant
    Filed: August 2, 2002
    Date of Patent: May 31, 2005
    Assignee: Freescale Semiconductor, Inc.
    Inventors: John L. Freeman, Jr., Raymond J. Balda, Robert A. Pryor, Joseph L. Petrucci, Jr., Robert J. Johnsen
  • Publication number: 20020190351
    Abstract: In a semiconductor manufacturing method, an emitter region (211) and a base enhancement region (207) are formed to provide linear voltage, capacitance and low resistance characteristics. In the manufacturing method, a semiconductor device (200) is formed on a silicon substrate layer (101) with an epitaxial layer (203). Trenches (233) are cut into the epitaxial layer (203) and filled with oxide (601) to provide reduced junction capacitance and reduced base resistance. The emitter region (211) and the base enhancement region (207) are simultaneously formed through an anneal process.
    Type: Application
    Filed: August 2, 2002
    Publication date: December 19, 2002
    Inventors: John L. Freeman, Raymond J. Balda, Robert A. Pryor, Joseph L. Petrucci, Robert J. Johnsen
  • Patent number: 6489211
    Abstract: A method of manufacturing a semiconductor component includes providing a composite substrate (300) with a dielectric portion and a semiconductor portion and growing an epitaxial layer (400) over the composite substrate. The epitaxial layer has a polycrystalline portion (402) over the dielectric portion of the composite substrate and also has a monocrystalline portion (401) over the semiconductor portion of the composite substrate. A first dopant is diffused into the monocrystalline portion of the epitaxial layer to form an emitter region in the monocrystalline portion of the epitaxial layer while a second dopant is simultaneously diffused into the monocrystalline portion of the epitaxial layer to form an enhanced portion of the base region.
    Type: Grant
    Filed: March 1, 2000
    Date of Patent: December 3, 2002
    Assignee: Motorola, Inc.
    Inventors: John L. Freeman, Jr., Raymond J. Balda, Robert A. Pryor, James D. Paulsen, Robert J. Johnsen
  • Patent number: 6121619
    Abstract: A method for predicting PMT failure in a gamma camera by generating historical data for each PMT in a gamma camera indicating high voltage gain values at which each PMT causes autotune failure. The historical data is analyzed to predict PMT failure accurately thereby allowing PMT maintenance prior to failure actually occurring.
    Type: Grant
    Filed: August 13, 1998
    Date of Patent: September 19, 2000
    Assignee: General Electric Company
    Inventors: Robert J. Johnsen, Nicholas Waterton, Burke D. Brunet
  • Patent number: 5155563
    Abstract: A semiconductor device having a low source inductance are fabricated by having a maximum of two sources each in contact with a region which makes contact to a substrate or back side of the device. The back side source contact also allows the device to be mounted directly to a grounded heatsink.
    Type: Grant
    Filed: March 18, 1991
    Date of Patent: October 13, 1992
    Assignee: Motorola, Inc.
    Inventors: Robert B. Davies, Robert J. Johnsen, Francine Y. Robb
  • Patent number: 5134448
    Abstract: A MOSFET having a back-side source contact and top-side gate and drain contacts is provided by a structure comprising superposed N.sup.+, N-, P-, N.sup.+ regions arranged between top and bottom surfaces of the semiconductor die. In a preferred implementation, two trenches are etched from the top surface to the P-, N.sup.+ interface. A buried P-, N.sup.+ short is provided in one trench and a gate dielectric and gate electrode are provided over the sidewall P- region exposed in the other trench. This creates a vertical MOSFET in which the N.sup.+ substrate forms the source region shorted to the P- body region in which the channel is created by the gate. Superior performance is obtained in RF grounded-source circuit applications.
    Type: Grant
    Filed: January 22, 1991
    Date of Patent: July 28, 1992
    Assignee: Motorola, Inc.
    Inventors: Robert J. Johnsen, Paul W. Sanders
  • Patent number: 5023196
    Abstract: A MOSFET having a back-side source contact and top-side gate and drain contacts is provided by a structure comprising superposed N.sup.+, N-,P-, N.sup.+ regions arranged between top and bottom surfaces of the semiconductor die. In a preferred implementation, two trenches are etched from the top surface to the P-, N.sup.+ interface. A buried P-, N.sup.+ short is provided in one trench and a gate dielectric and gate electrode are provided over the sidewall P- region exposed in the other trench. This creates a vertical MOSFET in which the N.sup.+ substrate forms the source region shorted to the P- body region in which the channel is created by the gate. Superior performance is obtained in RF grounded-source circuit applications.
    Type: Grant
    Filed: January 29, 1990
    Date of Patent: June 11, 1991
    Assignee: Motorola Inc.
    Inventors: Robert J. Johnsen, Paul W. Sanders