Patents by Inventor Robert J. Joynt

Robert J. Joynt has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250254951
    Abstract: Heterostructures having germanium-seeded, shear-strained silicon quantum wells are provided. Also provided are gate-controlled qubits based on the heterostructures, and quantum computing systems based on the qubits. The heterostructures include a quantum well of germanium-seeded silicon positioned between two quantum barriers of germanium or a silicon-germanium alloy. The silicon of the quantum well is under a shear strain and is seeded with germanium such that the germanium concentration in the quantum well has an oscillating profile.
    Type: Application
    Filed: August 2, 2023
    Publication date: August 7, 2025
    Inventors: Mark G. Friesen, Benjamin Woods, Mark A. Eriksson, Robert J. Joynt, Emily S. Joseph
  • Patent number: 11133388
    Abstract: Semiconductor heterostructures, methods of making the heterostructures, and quantum dots and quantum computation devices based on the heterostructures are provided. The heterostructures include a quantum well of strained silicon seeded with a relatively low concentration of germanium impurities disposed between two quantum barriers of germanium or a silicon-germanium alloy. The quantum wells are characterized in that the germanium concentration in the wells has an oscillating profile that increases the valley splitting in the conduction band of the silicon quantum well.
    Type: Grant
    Filed: July 23, 2020
    Date of Patent: September 28, 2021
    Assignee: Wisconsin Alumni Research Foundation
    Inventors: Robert J. Joynt, Mark G. Friesen, Mark A. Eriksson, Susan Nan Coppersmith, Donald E. Savage
  • Patent number: 6597010
    Abstract: Semiconductor dot devices include a multiple layer semiconductor structure having a substrate, a back gate electrode layer, a quantum well layer, a tunnel barrier layer between the quantum well layer and the back gate, and a barrier layer above the quantum well layer. Multiple electrode gates are formed on the multi-layer semiconductor with the gates spaced from each other by a region beneath which quantum dots may be defined. Appropriate voltages applied to the electrodes allow the development and appropriate positioning of the quantum dots, allowing a large number of quantum dots be formed in a series with appropriate coupling between the dots.
    Type: Grant
    Filed: March 8, 2002
    Date of Patent: July 22, 2003
    Assignee: Wisconsin Alumni Research Foundation
    Inventors: Mark A. Eriksson, Mark G. Friesen, Robert J. Joynt, Max G. Lagally, Daniel W. van der Weide, Paul Rugheimer, Donald E. Savage
  • Publication number: 20020179897
    Abstract: Semiconductor dot devices include a multiple layer semiconductor structure having a substrate, a back gate electrode layer, a quantum well layer, a tunnel barrier layer between the quantum well layer and the back gate, and a barrier layer above the quantum well layer. Multiple electrode gates are formed on the multi-layer semiconductor with the gates spaced from each other by a region beneath which quantum dots may be defined. Appropriate voltages applied to the electrodes allow the development and appropriate positioning of the quantum dots, allowing a large number of quantum dots be formed in a series with appropriate coupling between the dots.
    Type: Application
    Filed: March 8, 2002
    Publication date: December 5, 2002
    Inventors: Mark A. Eriksson, Mark G. Friesen, Robert J. Joynt, Max G. Lagally, Daniel W. van der Weide, Paul Rugheimer, Donald E. Savage