Patents by Inventor Robert J. Ko

Robert J. Ko has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Structure and method for providing reconfigurable emulation circuit
    Patent number: 5835751
    Abstract: A method and a structure provide emulation circuit implemented on a logic block module comprising clocked and unclocked field programmable logic devices (FPGAs). Software modules analyze the target logic circuit and impose delay constraints to require certain storage instances to be implemented on separate FPGAs so as to prevent hold time violation artifacts.
    Type: Grant
    Filed: July 11, 1997
    Date of Patent: November 10, 1998
    Assignee: Quickturn Design Systems, Inc.
    Inventors: Nang-Ping Chen, Robert J. Ko, Jeong-Tyng Li, Thomas B. Huang, Ming-Yang Wang
  • Methods for controlling timing in a logic emulation system
    Patent number: 5649167
    Abstract: A method and a structure for implementing integrated circuit designs into a plurality of clocked and unclocked reprogrammable logic circuits. Software structures analyze the target logic circuit, form clusters, partitions the integrated circuit design and implement the partitions into the clocked and unclocked reprogrammable logic circuits in order to prevent hold time violation artifacts.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: July 15, 1997
    Assignee: Quickturn Design Systems, Inc.
    Inventors: Nang-Ping Chen, Robert J. Ko, Jeong-Tyng Li, Thomas B. Huang, Ming-Yang Wang
  • Structure and method for providing a reconfigurable emulation circuit without hold time violations
    Patent number: 5475830
    Abstract: A method and a structure for implementing integrated circuit designs into a plurality of clocked and unclocked reprogrammable logic circuits. Software structures analyze the target logic circuit, form clusters, partition the integrated circuit design and implement the partitions into the clocked and unclocked reprogrammable logic circuits in order to prevent hold time violation artifacts.
    Type: Grant
    Filed: January 31, 1992
    Date of Patent: December 12, 1995
    Assignee: Quickturn Design Systems, Inc.
    Inventors: Nang-Ping Chen, Robert J. Ko, Jeong-Tyng Li, Thomas B. Huang, Ming-Yang Wang