Patents by Inventor Robert J Kushlis

Robert J Kushlis has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method and apparatus for implementing a bi-endian capable compiler
    Patent number: 8863103
    Abstract: A method of compiling code includes assigning an endian type to data. An endian flip operation is performed based on the endian type of the data and a target system. Other embodiments are described and claimed.
    Type: Grant
    Filed: May 11, 2009
    Date of Patent: October 14, 2014
    Assignee: Intel Corporation
    Inventors: Matthew J. Adiletta, Hugh Wilkinson, Robert J. Kushlis
  • Managing and implementing metadata in central processing unit using register extensions
    Patent number: 8635415
    Abstract: A set of default registers of a processor are expanded into metadata registers on the processor of a computer system. The default registers having stored thereon data, while metadata which is related to the data is stored separately on the metadata registers.
    Type: Grant
    Filed: September 30, 2009
    Date of Patent: January 21, 2014
    Assignee: Intel Corporation
    Inventors: Baiju V. Patel, Rajeev Gopalakrishna, Andrew F. Glew, Robert J. Kushlis, Don Alan Van Dyke, Joseph Frank Cihula, Asit K. Mallick, James B. Crossland, Gilbert Neiger, Scott Dion Rodgers, Martin Guy Dixon, Mark Jay Charney, Jacob (Koby) Gottlieb
  • MANAGING AND IMPLEMENTING METADATA IN CENTRAL PROCESSING UNIT USING REGISTER EXTENSIONS
    Publication number: 20110078389
    Abstract: A set of default registers of a processor are expanded into metadata registers on the processor of a computer system. The default registers having stored thereon data, while metadata which is related to the data is stored separately on the metadata registers.
    Type: Application
    Filed: September 30, 2009
    Publication date: March 31, 2011
    Inventors: Baiju V. Patel, Rajeev Gopalakrishna, Andrew F. Glew, Robert J. Kushlis, Don Alan Van Dyke, Joseph Frank Cihula, Asit K. Mallick, James B. Crossland, Gilbert Neiger, Scott Dion Rodgers, Martin Guy Dixon, Mark Jay Charney, Jocob Gottlieb
  • Method and apparatus for implementing a bi-endian capable compiler
    Publication number: 20090222800
    Abstract: A method of compiling code includes assigning an endian type to data. An endian flip operation is performed based on the endian type of the data and a target system. Other embodiments are described and claimed.
    Type: Application
    Filed: May 11, 2009
    Publication date: September 3, 2009
    Inventors: Matthew J. Adiletta, Hugh Wilkinson, Robert J. Kushlis
  • Method and apparatus for implementing a bi-endian capable compiler
    Patent number: 7552427
    Abstract: A method of compiling code includes assigning an endian type to data. An endian flip operation is performed based on the endian type of the data and a target system. Other embodiments are described and claimed.
    Type: Grant
    Filed: December 13, 2004
    Date of Patent: June 23, 2009
    Assignee: Intel Corporation
    Inventors: Matthew J Adiletta, Hugh Wilkinson, Robert J Kushlis
  • Processing a data packet
    Patent number: 7443836
    Abstract: A device and method for processing a data packet at a device are described. The device receives data packets and determines available memory in one or more of local memories of a plurality of execution threads. The device stores packet information in an available one of the local memories of the execution threads.
    Type: Grant
    Filed: June 16, 2003
    Date of Patent: October 28, 2008
    Assignee: Intel Corporation
    Inventors: Donald F. Hooper, Mark B. Rosenbluth, Gilbert Wolrich, Matthew J. Adiletta, Hugh M. Wilkinson, III, Robert J. Kushlis
  • Inter-procedure global register allocation method
    Patent number: 7069548
    Abstract: Embodiments of the present invention provide a method and system for optimizing processor register allocation. Variables from an acyclic call graph having a plurality of functions may be identified and a plurality of virtual registers may be created by assigning each of the identified variables to at least one virtual register. An interference graph may be constructed based on the plurality of virtual registers and may be colored with a plurality of physical registers. If the interference graph is not colorable, then at least one virtual register may be spilled from the interference graph.
    Type: Grant
    Filed: June 28, 2002
    Date of Patent: June 27, 2006
    Assignee: Intel Corporation
    Inventor: Robert J Kushlis
  • Processing a data packet
    Publication number: 20040252686
    Abstract: A device and method for processing a data packet at a device are described. The device receives data packets and determines available memory in one or more of local memories of a plurality of execution threads. The device stores packet information in an available one of the local memories of the execution threads.
    Type: Application
    Filed: June 16, 2003
    Publication date: December 16, 2004
    Inventors: Donald F. Hooper, Mark B. Rosenbluth, Gilbert Wolrich, Matthew J. Adiletta, Hugh M. Wilkinson, Robert J. Kushlis
  • Programming a multi-threaded processor
    Publication number: 20040034858
    Abstract: A computer instruction includes a declaration instruction that results in a variable name being associated with a memory location in one of a plurality of memories, the declaration instruction having a first field to specify the variable name, a second field to specify a one of the plurality of memory systems to associate with the variable name.
    Type: Application
    Filed: August 14, 2002
    Publication date: February 19, 2004
    Inventor: Robert J. Kushlis
  • Inter-procedure global register allocation method
    Publication number: 20040003385
    Abstract: Embodiments of the present invention provide a method and system for optimizing processor register allocation. Variables from an acyclic call graph having a plurality of functions may be identified and a plurality of virtual registers may be created by assigning each of the identified variables to at least one virtual register. An interference graph may be constructed based on the plurality of virtual registers and may be colored with a plurality of physical registers. If the interference graph is not colorable, then at least one virtual register may be spilled from the interference graph.
    Type: Application
    Filed: June 28, 2002
    Publication date: January 1, 2004
    Applicant: INTEL CORPORATION
    Inventor: Robert J. Kushlis