Abstract: A system and method are disclosed for capturing pre- and post-event data for random events using minimum power. Real-time data is captured and stored in a continuous loop in a segment of a first memory. Upon detection of a designated event, a second memory is powered-on and post-event data is stored to a segment of the second memory. After a designated data capture window, the second memory is powered-off and real-time data is captured in an unused segment of the first memory. The post-event data may be captured in the unused segment of the first memory and later transferred to the second memory. Auto-address logic monitors and controls the storage and retrieval of pre- and post-event in the first and second memory. An energy management system determines and controls which segments of the first and second memory should be powered-on or kept in the stasis mode to store event data.

Abstract: An integrated circuit containing a memory array, a redundancy circuit and a redundancy error correction circuit coupled to said redundancy circuit. A method for constructing a redundancy word which corresponds to each memory segment and a method for error checking the redundancy word during a memory access request.

Abstract: A system and method are disclosed for capturing pre- and post-event data for random events using minimum power. Real-time data is captured and stored in a continuous loop in a segment of a first memory. Upon detection of a designated event, a second memory is powered-on and post-event data is stored to a segment of the second memory. After a designated data capture window, the second memory is powered-off and real-time data is captured in an unused segment of the first memory. The post-event data may be captured in the unused segment of the first memory and later transferred to the second memory. Auto-address logic monitors and controls the storage and retrieval of pre- and post-event in the first and second memory. An energy management system determines and controls which segments of the first and second memory should be powered-on or kept in the stasis mode to store event data.

Abstract: An integrated circuit containing a memory array, a redundancy circuit and a redundancy error correction circuit coupled to said redundancy circuit. A method for constructing a redundancy word which corresponds to each memory segment and a method for error checking the redundancy word during a memory access request.

Abstract: A technique that provides width expansion of two CAMs of varying widths by combining match results from two CAMs by integrating the two CAMs. In one embodiment, a synchronizer circuit triggers the operation of an External Priority Encoder module which can be used to cascade two CAMs to form a wider CAM. When the External Priority Encoder module is used with the CAM, the External Priority Encoder module will receive MATCH signals and control signals from individual CAMs residing on either side, and will be triggered by the last arriving signal between two ports associated with two CAMs. In case one of the ports is disabled the External Priority Encoder module relies totally on the control signal from the other port for operation. The synchronizer circuit has the ability to handle mismatches between the CAMs as well as differentiating valid and invalid combinations between the CAMs.

Abstract: A technique that provides width expansion of two CAMs of varying widths by combining match results from two CAMs by integrating the two CAMs. In one embodiment, a synchronizer circuit triggers the operation of an External Priority Encoder module which can be used to cascade two CAMs to form a wider CAM. When the External Priority Encoder module is used with the CAM, the External Priority Encoder module will receive MATCH signals and control signals from individual CAMs residing on either side, and will be triggered by the last arriving signal between two ports associated with two CAMs. In case one of the ports is disabled the External Priority Encoder module relies totally on the control signal from the other port for operation. The synchronizer circuit has the ability to handle mismatches between the CAMs as well as differentiating valid and invalid combinations between the CAMs.

Abstract: A flip-flop circuit which includes a master section (1) having a pair of back to back connected inverters (5, 7) to form a latch circuit with their ground terminals connected together. The clock signal is coupled to the ground terminal of the inverters (5,7) to provide a negative gate to source voltage rather than an essentially zero gate to source voltage as used in prior art inverters to insure full turn off of the inverter transistors (40, 45) during their off periods and conserving power thereby. When the first phase of the clock signal goes high, the signal on the data line is fed to one side of the latch and the other side of the latch is coupled to ground or reference voltage. When the first phase of the clock then goes low, the signal from the data line is latched into the latch of the master section (1) and the other side of that latch is decoupled from ground.

Abstract: A logic module 400 for use in a field programmable gate array 100 can be selectively reconfigured to perform over 2,200 boolean combinational functions on output 431, to operate as a full adder with sum and carry outputs, or to perform the sequential function of a D latch or a D flipflop. Logic module 400 is comprised of 2-input multiplexers 500 and 600 which are used to form both the combinational and sequential circuits, thereby efficiently utilizing space on gate array 100.

Abstract: A signal transmission system (10) is provided that comprises a transmitter circuit (12) which transmits a signal through a transmission line (16) to a receiver circuit (14) using the current mode of signal transmission. A steady state current is supplied by a steady state current source (22). An active state current is provided by an active current source (20). A boost circuit (18) is provided to reduce delay associated with the transmission line (16) by increasing charge to the transmission line and providing additional discharge path from the transmission line during transitions of the signal propagating along transmission line (16).

Abstract: A flip-flop includes a data storage node for driving an inverter (62) and transfer gate (64) combination to transfer data stored on the data node (60) to a master storage node (66). A master cross-coupled latch (68) has two cross-coupled inverters (72) and (74) connected thereto such that the master storage node (66) is only connected to one side of the latch (68). The data node (66) directly drives a slave stage comprised of an inverter (76) and transfer gate (78) which in turn drives a slave storage node (80). The slave storage node (80) is connected to a slave cross-coupled latch (82) comprised of cross-coupled inverters (86) and (88). The slave storage node (80) comprises the Q-output of the inverter. The data is transferred to storage node (66) on the negative going edge of the clock signal and latched thereto on the positive going edge of the clock signal.

Abstract: A signal transmission system (10) is provided that comprises a transmitter circuit (12) which transmits a signal through a transmission line (16) to a receiver circuit (14) using the current mode of signal transmission. A steady state current is supplied by a steady state current source (22). An active state current is provided by an active current source (20). A boost circuit (18) is provided to reduce delay associated with the transmission line (16) by increasing charge to the transmission line and providing additional discharge path from the transmission line during transitions of the signal propagating along transmission line (16).

Abstract: A base cell for a CMOS gate array is provided with a plurality of N-channel transistors 10, 12, 14 with all such N-channel transistors coupled in series. A plurality of P-channel transistors 16, 18 coupled in series. These transistors are interconnected at the transistor level to form a partially prewired circuit. Specifically, the gates of two of the N-channel transistors 12, 14 are connected by polysilicon lead 28 to the gate of transistor 16. This configuration forms a circuit primitive which is well adapted for use as a base cell in a programmable array device.

Abstract: An adder-based base cell (10) is provided for field programmable gate arrays. The base cell (10) includes a first inverter (13) operable to receive a first input signal (A). A first NAND gate (12) is coupled to the first inverter (13) and is operable to receive a second input signal (B). A first 2:1 multiplexer (14) is coupled to the first NAND gate (12) and is operable to receive a third input signal (C). The output of the first 2:1 multiplexer (14) represents a first function (F1). A second inverter (17) is operable to receive a fourth input signal (D). A second NAND gate (16) is coupled to the second inverter (17) and is operable to receive a fifth input signal (E). An XOR gate (18) is coupled to the second NAND gate (16), is operable to receive a sixth input signal (F), and is coupled to the first 2:1 multiplexer (14). The output of the XOR gate represents a partial sum function (PS.sub.-- 1).

Abstract: A flip-flop designed for use in gate arrays following LSSD design rules. The flip-flop has a data input D and a scan data input SD which are gated by control signals fmc, fmc' to the flip-flop input terminal 18. The flip-flop input 18 is gated into a master flip-flop consisting of two inverters 30, 32 coupled back-to-back by a gate signal DMC which is valid when the desired input signal is gated to the flip-flop input 18. The master flip-flop is coupled to a slave flip-flop which is gated by a different control signal. The slave flip-flop consists of two inverters 44, 46 coupled back-to-back. Inverters 48, 50 coupled to the slave flip-flop provide a buffered output therefrom.

Abstract: Programmable circuitry (10) is provided including a plurality of logic modules (12) each having at least one input conductor (16). A nearest neighbor conductor (36) is fusibly coupled to output circuitry (25) of a selected logic module (12), the nearest neighbor conductor (36) intersecting the input conductor (16) of a nearest neighbor logic module (12). A fuse (40) disposed at the intersection of the nearest neighbor conductor (36) and the input conductor (16) of the nearest neighbor logic module (12) is provided for selectively establishing electrical coupling therebetween.

Abstract: A base cell for a CMOS gate array is provided with a first plurality of N-channel transistors 12, 14, 16 with two such N-channel transistors coupled in series. A first plurality of P-channel transistors 50, 52, 54 with two such P-channel transistors coupled in series. These transistors are interconnected at the transistor level to form a partially prewired circuit. Additional pairs of series connected N-channel transistors (18, 20), (22, 24) and pairs of series connected P-channel transistors (56, 58), (60, 62) are also provided and are interconnected at the transistor level to form additional partially prewired circuits. By adding additional levels of wiring 100, 102, the base cell can be finally wired to form a plurality of different logic circuits.

Abstract: A base cell for a CMOS gate array is provided with a plurality of N-channel transistors 10 and a plurality of P-channel transistors 12. These transistors are interconnected at the transistor level to form a partially prewired circuit. Additional N-channel (14) and P-channel (70, 72) transistors are included in the base cell at least some of which are larger in size than those in the plurality of N-channel transistors 10 or the plurality of P-channel transistors 12. These larger size transistors are used as output drivers to send the logical output signal of the cell to another cell.