Abstract: A band-gap voltage reference forming part of a CMOS IC chip. A .DELTA.V.sub.BE voltage is developed by stacked pairs of parasitic bipolar transistors, with the transistors of each pair operated at different current densities. MOS buffer transistors are connected at corresponding ends of the stacks where the .DELTA.V.sub.BE voltage is developed. The bipolar transistors are driven by MOS current sources.

Abstract: The invention provides a circuit which substantially cancels the input bias current of an operational amplifier having a cascoded NPN-PNP inmput stage. The compensation circuit comprises three transistors. A first NPN transistor is coupled to the input stage such that its collector is coupled to the positive voltage source of the operational amplifier and its emitter is coupled to the emitter of the dual-collector transistor of the input stage. The second transistor, a PNP transistor, has its base coupled to the base of the dual-collector transistor and its collector coupled to the bases of both of the NPN transistors of the input stage, which form the inputs of the operational amplifier. This PNP transistor's emitter is coupled to the collector of a third transistor which is a dual-collector PNP transistor. A third transistor has an emitter coupled to the positive voltage source of the operational amplifier and a base coupled to the base of the NPN transistor of the compensation circuitry.

Abstract: A voltage reference source for supplying one or more reference voltages to load circuitry. The reference source comprises an ungrounded voltage reference cell (20) floated between two power supply levels (Vcc and Vee), and an operational amplifier (22) whose non-inverting input (terminal 9) may be connected to sense the voltage of the load circuit's ground node. The inverting input of the op amp (terminal 10) may be connected to various nodes (6, 8, 11) in the reference cell; the voltage on the selected node is forced to match the sensed ground voltage and that node thus becomes an internal ground reference point. The high input impedance of the op amp (22) limits the current in the ground sensing path to a very low value, such as about 10 nA. Consequently, very little voltage is developed in the leads from the load circuit's ground node to the op amp input. The floating reference cell (20) has a resistive divider (48, 50) across its output.

Abstract: A band-gap voltage reference forming part of a CMOS IC chip. A .DELTA.V.sub.BE voltage is developed by stacked pairs of parasitic bipolar transistors, with the transistors of each pair operated at different current densities. MOS buffer transistors are connected at corresponding ends of the stacks where the .DELTA.V.sub.BE voltage is developed. The bipolar transistors are driven by MOS current sources.