Abstract: The present invention relates to a memory circuit including an array of inversion controlled switches arranged in an arbitrary number of rows and columns. Each inversion controlled switch is provided with emitter, base and collector terminals, and is characterized by first and second impedance states between its emitter and collector terminals.

Abstract: An illustrative embodiment of the invention provides a substantially non-destructive interrogation circuit for a memory cell such as a variable threshold insulated gate field effect memory transistor device whereby the circuit generates a fixed current for interrogation of the memory transistor such that the disturb voltage, the voltage impressed across the insulator of the memory transistor during interrogation, is minimized and is a function of the current and the gain of the memory device and not the threshold of the memory device. Moreover the disturb voltage is readily calculable and is equal for all interrogations and, therefore, enables one to calculate the maximum number of interrogations of a memory cell before the disturb voltage destroys the memory threshold of the memory cell and rewriting of the data therein must be performed. In addition, a sense latch circuit provides means for sensing the memory data of the memory cell without applying an additional disturb potential to the device.

Abstract: The decoder buffer is utilized in a memory system for an array of variable threshold MNOS transistor memory cells arranged in word rows. The gate electrodes of the memory transistors comprising each word row is coupled via a word line to the output of a decoder buffer. Inputs to the decoder buffers are provided from address decoder and inverter circuits in response to memory address inputs. FET control circuitry is included for selectively providing operating voltages to the decoder buffers in accordance with the various memory functions performed. Each decoder buffer comprises first, second and third fixed threshold field effect transistors, the first and second transistors being serially connected with respect to each other, forming a junction therebetween which is coupled to the associated one of the memory word lines.

Abstract: A monolithic integrated circuit, fully decoded memory comprises a rectangular array of variable threshold field effect transistors organized into a plurality of multi-bit words. Binary address inputs to the memory are decoded by a field effect transistor decoder into a plurality of word selection lines each of which activates an address buffer circuit. Each address buffer circuit, in turn, drives a word line of the memory array. In accordance with the word line selected by the decoder the activated buffer circuit directs reading or writing voltages to the transistors comprising the memory words. All of the buffer circuits additionally are connected to a common terminal for clearing all of the memory transistors to a predetermined state by the application to the common terminal of a large magnitude voltage of a predetermined polarity.