Abstract: An improved method and apparatus for encrypting and scrambling information cells transmitted on a telephone system local loop from a central office to a plurality of user premises networks via a shared medium passive optical network. Prior to transmission, the information cell is encrypted for security purposes and scrambled to improve its transmission properties by modulo 2 addition of the information cell and a combined encryption and scrambling sum pattern. At the other end of the passive optical network which is connected to user premises networks, the received encrypted and scrambled information cells are used to generate a processed cell by the modulo 2 addition of the received cell and a combined decryption and descramble sum pattern.

Abstract: The present invention provides a telecommunication network utilizing a passive optical network connecting a plurality of network terminations to a local exchange. Information cells and commands are transmitted on the network by the local exchange to all the network terminations. The information cells and commands contain routing address information for the particular network termination to which the information cell or command is destined. The address information contains the address of the destination network termination and additional identifier bits to facilitate encryption of the address information for security and privacy of traffic behavior without producing misdelivery occurrences. In addition, a system for repeatedly changing encryption patterns for the network terminations which detects misdelivery conditions is provided.

Abstract: As shown in FIG. 2 an ATD multiplexer (1-i) comprises a congestion detector (34) for detecting internal traffic congestion when a data cell stream is transferred from one of the two data inputs (4, 5) to the data output (6). If internal traffic congestion occurs, congestion signal transmitter (36) will supply a congestion signal. An upstream ATD multiplexer (1-j) will receive this congestion signal as an external congestion signal through congestion signal receiver (37) and in response thereto blocks one of its two data inputs (4, 5). In this fashion the data supply to ATD multiplexer (1-i) will be restricted.If the data supply to ATD multiplexer (1-i) is restricted to such an extent that internal traffic congestion no longer occurs in ATD multiplexer (1-i), the blocking of the blocked data input in ATD multiplexer (1-j) will be removed in a delayed manner.

Abstract: A digital Phase-Locked Loop (PLL), comprising a voltage-controlled oscillator (VCO) and a phase meter including a delay line with taps, wherein phase measurements are effected by sending a pulse through the delay line and determining the location of this pulse in the delay line at the rate of the output signal of the VCO. This location is determined by a processing circuit connected to the taps, which circuit generates in response to the location found a VCO control signal corresponding therewith.

Abstract: A switch matrix for telecommunication including change-over switches which can be used for both analog and digital signal transmission. Each change-over switch includes a selector circuit, an input and an output stage. The output stage generally includes two transistors coupled in a push-pull arrangement which are connected directly to the supply voltage allowing the capacitive load of the switch to be charged or discharged rapidly. Also, the Miller effect of the internal base-collector capacitance is absent. Consequently, a large frequency range (to approximately 3 GHz) is realized for analog use, and a switch rate of approximately 2 Gb/s is attainable for digital use.

Abstract: A telephone signalling receiver comprising speech detectors for respective voice-frequency signalling components of push-button (TDK) signals which are in a frequency band divided into lower and upper frequency subgroups. Each detector calculates the Discrete Fourier Transform (DFT) of the corresponding signal frequency component, the frequency characteristic of such detector having a main lobe for such signalling frequency component and two side lobes. Such calculation employs DFT product coefficients calculated for the lower and upper frequency subgroups and which are stored in memories, such coefficients being for particular Kaiser-Bessel window functions and for pairs of frequencies in the lower and higher subgroups. The coefficients are selected so that the peaks of the side lobes are lower, such as 6 dB below, the peaks of the associated main lobes.

Abstract: A clock signal arrangement comprises two phase-controlled loop (PLL) circuits each producing a regenerated clock signal c and r, respectively and a high-frequency oscillator signal, two time window signal generators each connected to one of the PLL circuits and also a logic circuit connected to the time window signal generators. The clock signal arrangement has for its object the regeneration of a clock signal which has a very high degree of accuracy as regards its frequency and phase. To that end, time window signals whose mutual position is a measure of the phase difference between the regenerated clock signals and whose width depends on the period duration of the oscillator signals are generated in each of the time window signal generators. In the logic circuit the time window signals clock one of the clock signals, which is only conveyed to an output terminal of the clock signal arrangement if the phase difference is less than half the duration of the period.

Abstract: A clock signal regenerator comprising a frequency control loop (1, 2, 3, 4) which comprises a variable-frequency clock signal generator (2) used in digital telephone exchanges, when a local clock signal must be generated from incoming clock signals (1-1, 1-N). The clock signal regenerator comprises a very stable auxiliary signal generator (9) and a first difference signal producer (11) for determining the frequency difference between the generated clock signal and the auxiliary signal. This frequency difference is determined periodically and written into a storage device (13). In addition, the regenerator comprises a second difference signal producer (14) in which the difference is determined between a new frequency difference determined in the first difference signal producer (11) and the preceding frequency difference stored in the storage arrangement (13). After the incoming clock signals (1-1, . . .