Abstract: A CPU initializes pluggable adapters with built-in identity and conditional ROS and complies a Hardware First Level Interrupt Handler (HFLIH) table of identity against status register address and a Software First Level Interrupt Handler (HFLIH) table of identity against on-board system function. It stores the tables with a control module in enabled memory on the keyboard adapter. Conditional ROS is enabled on a given adapter receiving a broadcast of its own identity. Adapter interrupts are ORed. HFLIH is stepped through by the control module to access adapter status sequentially, servicing each adapter in turn from its ROS, using its broadcast identity. The enabled adapter appears as a single entity to the central processor and occupies a single window in the address space which is common to all of the adapters but used by only one at a time. System functions are accessed via HFLIH.