Abstract: A single-photon avalanche diode (SPAD) device may include a semiconductor substrate having a first conductivity type, a deep well region in the semiconductor substrate having a second conductivity type different than the first conductivity type, and a multiplication region in the deep well region having the second conductivity type. The SPAD device may further include a central active region on the multiplication region and having the first conductivity type, a guard ring surrounding the central region and the multiplication region and having the first conductivity type, and a superlattice layer adjacent an interface between the multiplication region and the guard ring. The superlattice layer may include stacked groups of layers, with each group of layers comprising stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.

Abstract: A single-photon avalanche diode (SPAD) device may include a semiconductor substrate having a first conductivity type, a deep well region in the semiconductor substrate having a second conductivity type different than the first conductivity type, and a multiplication region in the deep well region having the second conductivity type. The SPAD device may further include a central active region on the multiplication region and having the first conductivity type, a guard ring surrounding the central region and the multiplication region and having the first conductivity type, and a superlattice layer adjacent an interface between the multiplication region and the central active region. The superlattice layer may include stacked groups of layers, with each group of layers including stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.

Abstract: A method for making a single-photon avalanche diode (SPAD) device may include forming a deep well region in a semiconductor substrate having a second conductivity type different than the first conductivity type, and forming a multiplication region in the deep well region having the second conductivity type. The method may further include forming a central active region on the multiplication region and having the first conductivity type, forming a guard ring surrounding the central region and the multiplication region and having the first conductivity type, and forming a superlattice layer adjacent an interface between the multiplication region and the central active region. The superlattice layer may include stacked groups of layers, with each group of layers comprising stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.

Abstract: A method for making a single-photon avalanche diode (SPAD) device may include forming a deep well region in a semiconductor substrate having a first conductivity type, the deep well region having a second conductivity type different than the first conductivity type. The method may further include forming a multiplication region in the deep well region having the second conductivity type, forming a central active region on the multiplication region and having the first conductivity type, forming a guard ring surrounding the central region and the multiplication region and having the first conductivity type, and forming a superlattice layer adjacent an interface between the multiplication region and the guard ring. The superlattice layer may include stacked groups of layers, each including a stacked base semiconductor monolayers defining a base semiconductor portion, and a non-semiconductor monolayer(s) constrained within a crystal lattice of adjacent base semiconductor portions.

Abstract: A method for making an LDMOS device may include forming a trench in a semiconductor layer, and forming a superlattice liner in the trench. The superlattice liner may include stacked groups of layers, with each group of layers comprising stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer, and each at least one non-semiconductor monolayer of each group of layers being constrained within a crystal lattice of adjacent base semiconductor portions. The method may further include forming a drift region in the semiconductor layer surrounding the trench, forming a shallow trench isolation (STI) region within the trench and separated from the drift region by the superlattice liner, forming spaced-apart source and drain regions in the semiconductor layer on opposite sides of the trench, and forming a gate on the semiconductor layer between the source and drain regions.

Abstract: A laterally-diffused metal-oxide semiconductor (LDMOS) device may include a semiconductor layer having a trench therein, and a superlattice liner in the trench. The superlattice liner may include stacked groups of layers, with each group of layers comprising stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer, and each at least one non-semiconductor monolayer of each group of layers being constrained within a crystal lattice of adjacent base semiconductor portions. The LDMOS may further include a shallow trench isolation (STI) region within the trench, spaced-apart source and drain regions in the semiconductor layer on opposite sides of the trench, a gate on the semiconductor layer between the source and drain regions, and a drift region in the semiconductor layer surrounding the trench and separated from the STI region by the superlattice liner.

Abstract: A method for making a semiconductor device may include growing 28Si on a semiconductor layer, intermixing the 28Si in the semiconductor layer, and thinning the semiconductor layer after intermixing. The method may further include repeating growing, intermixing, and thinning until a concentration of 28Si in the semiconductor layer reaches a target concentration.

Abstract: A semiconductor gate-all-around (GAA) device may include a semiconductor substrate, source and drain regions on the semiconductor substrate, a plurality of semiconductor nanostructures extending between the source and drain regions, a gate surrounding the plurality of semiconductor nanostructures in a gate-all-around arrangement, and a dopant diffusion liner adjacent at least one of the source and drain regions and comprising a first superlattice. The first superlattice may include a plurality of stacked groups of layers, with each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.

Abstract: An electronic device may include a poled region having a net electrical dipole moment and including a semiconductor layer and at least one non-semiconductor monolayer constrained within a crystal lattice of the silicon layer. The electronic device may further include a plurality of spaced apart alternating N-type and P-type regions within the poled region to align the net electrical dipole moment of the poled region, and at least one electrode associated with the poled region. The poled region may be a superlattice, for example.

Abstract: A method for making an electronic device may include forming a semiconductor region comprising a semiconductor layer and at least one non-semiconductor monolayer constrained within a crystal lattice of the silicon layer. The method may also include forming a plurality of spaced apart alternating N-type and P-type regions within the semiconductor region, forming at least one electrode associated with the semiconductor region, and poling the semiconductor region to align a net electrical dipole moment thereof using the plurality of spaced apart alternating N-type and P-type regions. The poled region may include a superlattice.

Abstract: A radio frequency (RF) semiconductor device may include a semiconductor-on-insulator substrate, and an RF ground plane layer on the semiconductor-on-insulator substrate including a conductive superlattice. The conductive superlattice may include stacked groups of layers, with each group of layers comprising stacked doped base semiconductor monolayers defining a doped base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent doped base semiconductor portions. The RF semiconductor device may further include a body above the RF ground plane layer, spaced apart source and drain regions adjacent the body and defining a channel region in the body, and a gate overlying the channel region.

Abstract: A semiconductor gate-all-around (GAA) device may include a semiconductor substrate, source and drain regions on the semiconductor substrate, a plurality of semiconductor nanostructures extending between the source and drain regions, a gate surrounding the plurality of semiconductor nanostructures in a gate-all-around arrangement, and a dopant diffusion liner adjacent at least one of the source and drain regions and comprising a first superlattice. The first superlattice may include a plurality of stacked groups of layers, with each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.

Abstract: A radio frequency (RF) semiconductor device may include a semiconductor-on-insulator substrate, and an RF ground plane layer on the semiconductor-on-insulator substrate including a conductive superlattice. The conductive superlattice may include stacked groups of layers, with each group of layers comprising stacked doped base semiconductor monolayers defining a doped base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent doped base semiconductor portions. The RF semiconductor device may further include a body above the RF ground plane layer, spaced apart source and drain regions adjacent the body and defining a channel region in the body, and a gate overlying the channel region.

Abstract: A semiconductor device may include a substrate, a stack of alternating gate and nanostructure layers above the substrate, and a first superlattice laterally adjacent the stack on a first side thereof and extending from the substrate to an upper surface of the stack to define a first source/drain region. The first superlattice may include a plurality of stacked groups of layers, with each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The non-semiconductor monolayers of the first superlattice may be arranged along growth rings extending outwardly from respective adjacent nanostructure layer portions.

Abstract: A method for making a semiconductor device may include forming a stack of alternating gate and nanostructure layers above a substrate, and forming a first superlattice laterally adjacent the stack on a first side thereof and extending from the substrate to an upper surface of the stack to define a first source/drain region. The first superlattice may include a plurality of stacked groups of layers, with each group of layers including stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The non-semiconductor monolayers of the first superlattice may be arranged along growth rings extending outwardly from respective adjacent nanostructure layer portions.

Abstract: A semiconductor device may include a semiconductor substrate and a superlattice layer on the semiconductor substrate. The superlattice layer may include a plurality of stacked groups of layers, with each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The semiconductor device may also include a piezoelectric layer on the superlattice layer and comprising a Group III-N semiconductor.

Abstract: A semiconductor device may include a semiconductor substrate and a superlattice layer on the semiconductor substrate. The superlattice layer may include a plurality of stacked groups of layers, with each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The semiconductor device may further include a Group III-N semiconductor stack including a plurality of layers of Group III-N semiconductor layers above the superlattice layer.

Abstract: A method for making a semiconductor device may include forming a superlattice layer on a first substrate and including a plurality of stacked groups of layers, with each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base silicon portions. The method may further include forming a Group III-N semiconductor stack comprising a plurality of layers of Group III-N semiconductor layers above the superlattice layer, and separating the Group III-N semiconductor stack from the first substrate at the superlattice layer.

Abstract: A method for making a semiconductor device may include forming a first superlattice layer on a semiconductor substrate. The first superlattice layer may include a plurality of stacked groups of layers, with each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The method may further include forming a first device layer on the first superlattice layer and comprising silicon, forming a second device layer on the first superlattice layer laterally adjacent the first device layer, with the second device layer comprising a Group III-N semiconductor, forming a first device on the first device layer, and forming a second device on the second device layer.

Abstract: A method for making a semiconductor device may include forming a semiconductor substrate, and forming a superlattice layer on the semiconductor substrate and including a plurality of stacked groups of layers. Each group of layers may including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The method may also include forming a Group III-N semiconductor stack comprising a plurality of layers of Group III-N semiconductor layers above the superlattice layer.