Abstract: A high accuracy method for transistor-level static timing analysis is disclosed. Accurate static timing verification requires that individual gate and interconnect delays be accurately calculated. At the sub-micron level, calculating gate and interconnect delays using delay models can result in reduced accuracy. Instead, the proposed method calculates delays through numerical integration using an embedded circuit simulator. It takes into account short circuit current and carefully chooses the set of conditions that results in a tight upper bound of the worst case delay for each gate. Similar repeating transistor configurations of gates in the circuit are automatically identified and a novel interpolation based caching scheme quickly computes gate delays from the delays of similar gates. A tight object code level integration with a commercial high speed transistor-level circuit simulator allows efficient invocation of the simulation.

Abstract: A computer-implemented method abstracts the timing constraints for latches internal to a digital logic circuit, resulting in a clock characterization model. Timing information (such as propagation delays, set-up and hold requirements) for latches and combinational logic circuits contained in a digital logic circuit are received, as is a description of a class of clock scheme for clocking the circuit. Clock parameters are selected for the clock scheme class. The internal timing constraints for the digital logic circuit are expressed as timing constraint expressions which are a function of the clock parameters. The expressions are combined to define a region of feasible clock operation expressed in terms of the clock parameters.

Abstract: A method and mechanism for performing a timing analysis on virtual component blocks, which is an abstraction of a circuit block is provided. A set of modes for a circuit block are identified, where a mode is a set of meaningful control input values. Each functionally meaningful or useful control input combination is applied to the circuit block. For each control input combination applied, a delay for each data input/output path and each control input/output path not passing through a blocked circuit node for the applied combination of control inputs is calculated. The delay information for the data paths and control paths is stored within a timing model. The delay information may include a maximum or minimum delay for the circuit block. The timing of sequential circuit blocks may also characterized using the methods and mechanisms herein.

Abstract: A system and method for performing a timing analysis on virtual component blocks or other circuit models is provided wherein functional information obtained from the circuit's control inputs and their useful combinations is used to improve accuracy. The control inputs and data inputs for a circuit block are identified. Each functionally meaningful or useful control input combination is applied to the circuit block, and the topological delay for the data inputs are determined only along the paths that are not blocked by the control inputs. The delays along paths that are blocked are ignored. The analysis is further augmented by determining the topological delay for all paths originating at control inputs, without regard to blocking of paths, so as to reduce the chance for possible underestimation of delays from the data inputs.

Abstract: A high accuracy method for transistor-level static timing analysis is disclosed. Accurate static timing verification requires that individual gate and interconnect delays be accurately calculated. At the sub-micron level, calculating gate and interconnect delays using delay models can result in reduced accuracy. Instead, the proposed method calculates delays through numerical integration using an embedded circuit simulator. It takes into account short circuit current and carefully chooses the set of conditions that results in a tight upper bound of the worst case delay for each gate. Similar repeating transistor configurations of gates in the circuit are automatically identified and a novel interpolation based caching scheme quickly computes gate delays from the delays of similar gates. A tight object code level integration with a commercial high speed transistor-level circuit simulator allows efficient invocation of the simulation.

Abstract: A computer-implemented method abstracts the timing constraints for latches internal to a digital logic circuit, resulting in a clock characterization model. Timing information (such as propagation delays, set-up and hold requirements) for latches and combinational logic circuits contained in a digital logic circuit are received, as is a description of a class of clock scheme for clocking the circuit. Clock parameters are selected for the clock scheme class. The internal timing constraints for the digital logic circuit are expressed as timing constraint expressions which are a function of the clock parameters. The expressions are combined to define a region of feasible clock operation expressed in terms of the clock parameters.

Abstract: An automatic process of compacting or "flattening" a hierarchical multi-level logic design for more efficient timing analysis purposes while using electronic design automation tools, the hierarchical multi-level logic design having at least one higher level logic design including at least one instance, but typically a plurality of instances, of a lower level logic design. The process includes creating a file for storing logic design data defining a lower level logic design and timing analysis input data for the lower level logic design, deleting selected logic design data from the file wherein the deleted data represents all internal paths and components of the lower level logic which are not connected to the higher level logic design, thereby leaving only data for external paths and components of the lower level logic design connected to the higher level logic design in the file.

Abstract: The scan cycle in a programmable logic controller is constructed so as to allow the PLC users program to execute an instruction to assign a user program section to which the PLC system is to transfer control upon the occurance of an instruction-specified event. Also allowed is the de-assignment of a user program section from an instruction-specified event. Moreover, the interrupt may happen at any portion of the PLC scan cycle and not merely at compilation time. This thereby allows for dynamically presetting values of characters and the like as well as pipelining of interrupts in the PLC.

Abstract: A system and method for detecting timing design errors in a design having multiple state devices clocked by multiple clock signals. The design includes at least first and second state devices clocked by first and second clock signals. A reference time is designated, and a time differential between successive triggering edges of the first and second clock signals is calculated. The time of the occurrence of each triggering edge of the first and second clock signal is calculated with respect to the reference time, rather than directly with respect to each other. The calculation of the time differential includes storing a period time and a time offset the first and second clock signals. The time offsets are time durations measured from the reference time to the first pulse of each of the first and second clock signals that occur simultaneously with, or subsequent to, the reference time.

Abstract: A method and apparatus for efficiently optimizing a circuit design by substituting identified cells within the circuit design with logically equivalent cells having different drive strengths. The present invention eliminates the need to update the design database and to place and route the circuit design during each design iteration. Rather, an improved extraction tool is provided which incorporates a cell substitution list, and updates the RC file therefrom. The updated RC file is used by the timing analysis tool to determine if the updated design will meet the design specification. After the design meets the design specification, a final place and route may be performed.

Abstract: A high speed programmable logic controller is taught. Briefly stated a Programmable Logic Controller having memory, a microprocessor and a Co-Processor are operatively interconnected using a Harvard style architecture therefore having separate data and instruction busses. The Co-Processor acts as a Boolean Processor and is therefore able to simultaneously perform instruction fetches and executions thereby resulting in substantially increased overall speed of the PLC and therefore allowing for fast process control.