Patents by Inventor Robert J. Purtell
Robert J. Purtell has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7504336Abstract: The present invention provides a method of fabricating semiconductor device comprising at least one field effect transistor (FET) having source and drain (S/D) metal silicide layers with intrinsic tensile or compressive stress. First, a metal layer containing a silicide metal M is formed over S/D regions of a FET, followed by a first annealing step to form S/D metal silicide layers that comprise a metal silicide of a first phase (MSix). A silicon nitride layer is then formed over the FET, followed by a second annealing step. During the second annealing step, the metal silicide is converted from the first phase (MSix) into a second phase (MSiy) with x<y. The metal silicide conversion causes either volumetric shrinkage or expansion in the S/D metal silicide layers of the FET, which in turn generates intrinsic tensile or compressive stress in the S/D metal silicide layers under confinement by the silicon nitride layer.Type: GrantFiled: May 19, 2006Date of Patent: March 17, 2009Assignee: International Business Machines CorporationInventors: Robert J. Purtell, Henry K. Utomo, Yun-Yu Wang, Haining S. Yang
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Patent number: 7485572Abstract: A method of forming silicide contacts for semiconductor devices includes subjecting a silicon containing semiconductor wafer to a degas treatment at a temperature of about 400° C., transferring the semiconductor wafer from a degas chamber to a deposition chamber, depositing a cobalt layer over the wafer at a point in time when the semiconductor wafer has cooled to temperature range of about 275-300° C., depositing a cap layer over the cobalt layer, and annealing the semiconductor wafer so as to create silicide contacts at portions on the wafer where cobalt is formed over silicon.Type: GrantFiled: September 25, 2006Date of Patent: February 3, 2009Assignee: International Business Machines CorporationInventors: Anita Madan, Robert J. Purtell, Keith Kwong Hon Wong
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Publication number: 20090029549Abstract: A method forms a first layer over a second layer that comprises silicon. A mask is formed and patterned over the insulator layer. Then, a heavy inert gas such as Xenon (Xe) is implanted through the openings in the mask, through the insulator layer, and into the regions of the silicon layer that are below the opening in the mask. The portions of the insulator layer that are below the openings in the mask are etched away and the mask is removed. A metal or metal alloy layer is formed over the first layer and the exposed regions of the second layer. At least the second layer is heated in a silicide process such that the metal and the exposed regions of the second layer combine to form silicide regions. After this, any remaining metal material can be removed to remove to leave the silicide regions adjacent non-silicide regions of the second layer.Type: ApplicationFiled: July 23, 2007Publication date: January 29, 2009Inventors: Oh-Jung Kwon, Robert J. Purtell, Viraj Y. Sardesai
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Patent number: 7456095Abstract: A method and apparatus are provided in which non-directional and directional metal (e.g. Ni) deposition steps are performed in the same process chamber. A first plasma is formed for removing material from a target; a secondary plasma for increasing ion density in the material is formed in the interior of an annular electrode (e.g. a Ni ring) connected to an RF generator. Material is deposited non-directionally on the substrate in the absence of the secondary plasma and electrical biasing of the substrate, and deposited directionally when the secondary plasma is present and the substrate is electrically biased. Nickel silicide formed from the deposited metal has a lower gate polysilicon sheet resistance and may have a lower density of pipe defects than NiSi formed from metal deposited in a solely directional process, and has a lower source/drain contact resistance than NiSi formed from metal deposited in a solely non-directional process.Type: GrantFiled: October 3, 2005Date of Patent: November 25, 2008Assignee: International Business Machines CorporationInventors: Keith Kwong Hon Wong, Robert J. Purtell
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Publication number: 20080268604Abstract: Methods for fabricating a heterojunction bipolar transistor having a raised extrinsic base is provided in which the base resistance is reduced by forming a silicide atop the raised extrinsic base that extends to the emitter region in a self-aligned manner. The silicide formation is incorporated into a BiCMOS process flow after the raised extrinsic base has been formed. The present invention also provides a heterojunction bipolar transistor having a raised extrinsic base and a silicide located atop the raised extrinsic base. The silicide atop the raised extrinsic base extends to the emitter in a self-aligned manner. The emitter is separated from the silicide by a spacer.Type: ApplicationFiled: May 28, 2008Publication date: October 30, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Peter J. Geiss, Marwan H. Khater, Qizhi Liu, Randy W. Mann, Robert J. Purtell, BethAnn Rainey, Jae-Sung Rieh, Andreas D. Stricker
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Publication number: 20080220604Abstract: Disclosed is a structure and method for tuning silicide stress and, particularly, for developing a tensile silicide region on a gate conductor of an n-FET in order to optimize n-FET performance. More particularly, a first metal layer-protective cap layer-second metal layer stack is formed on an n-FET structure. However, prior to the deposition of the second metal layer, the protective layer is exposed to air. This air break step alters the adhesion between the protective cap layer and the second metal layer and thereby, effects the stress imparted upon the first metal layer during silicide formation. The result is a more tensile silicide that is optimal for n-FET performance.Type: ApplicationFiled: April 4, 2008Publication date: September 11, 2008Applicant: International Business Machines CorporationInventors: Robert J. Purtell, Keith Kwong Hon Wong
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Patent number: 7417290Abstract: Disclosed is a structure and method for tuning silicide stress and, particularly, for developing a tensile silicide region on a gate conductor of an n-FET in order to optimize n-FET performance. More particularly, a first metal layer-protective cap layer-second metal layer stack is formed on an n-FET structure. However, prior to the deposition of the second metal layer, the protective layer is exposed to air. This air break step alters the adhesion between the protective cap layer and the second metal layer and thereby, effects the stress imparted upon the first metal layer during silicide formation. The result is a more tensile silicide that is optimal for n-FET performance.Type: GrantFiled: January 9, 2006Date of Patent: August 26, 2008Assignee: International Business Machines CorporationInventors: Robert J. Purtell, Keith Kwong Hon Wong
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Publication number: 20080164540Abstract: A method and an apparatus are provided in which non-directional and directional metal (e.g. Ni) deposition steps are performed in the same process chamber. A first plasma is formed for removing material from a target; a secondary plasma for increasing ion density in the material is formed in the interior of an annular electrode (e.g. a Ni ring) connected to an RF generator. Material is deposited non-directionally on the substrate in the absence of the secondary plasma and electrical biasing of the substrate, and deposited directionally when the secondary plasma is present and the substrate is electrically biased. Nickel silicide formed from the deposited metal has a lower gate polysilicon sheet resistance and may have a lower density of pipe defects than NiSi formed from metal deposited in a solely directional process, and has a lower source/drain contact resistance than NiSi formed from metal deposited in a solely non-directional process.Type: ApplicationFiled: March 17, 2008Publication date: July 10, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Keith Kwong Hon Wong, Robert J. Purtell
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Publication number: 20080156265Abstract: A method and an apparatus are provided in which non-directional and directional metal (e.g. Ni) deposition steps are performed in the same process chamber. A first plasma is formed for removing material from a target; a secondary plasma for increasing ion density in the material is formed in the interior of an annular electrode (e.g. a Ni ring) connected to an RF generator. Material is deposited non-directionally on the substrate in the absence of the secondary plasma and electrical biasing of the substrate, and deposited directionally when the secondary plasma is present and the substrate is electrically biased. Nickel silicide formed from the deposited metal has a lower gate polysilicon sheet resistance and may have a lower density of pipe defects than NiSi formed from metal deposited in a solely directional process, and has a lower source/drain contact resistance than NiSi formed from metal deposited in a solely non-directional process.Type: ApplicationFiled: March 13, 2008Publication date: July 3, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Keith Kwong Hon Wong, Robert J. Purtell
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Publication number: 20080156257Abstract: A cluster tool is provided for the implementing of a clustered and integrated surface pre-cleaning of the surface of semiconductor devices. More particularly, there is provided a cluster tool and a method of utilization thereof in an integrated semiconductor device surface pre-cleaning, which is directed towards a manufacturing aspect in which a chamber for performing a dry processing chemical oxide removal (COR) on the semiconductor device surface is clustered with other tools, such as a metal deposition tool for silicide or contact formation, including the provision of a vacuum transfer module in the cluster tool.Type: ApplicationFiled: October 16, 2007Publication date: July 3, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Sadanand V. Deshpande, Ying Li, Kevin E. Mello, Renee T. Mo, Wesley C. Natzle, Kirk D. Peterson, Robert J. Purtell
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Patent number: 7390721Abstract: Methods for fabricating a heterojunction bipolar transistor having a raised extrinsic base is provided in which the base resistance is reduced by forming a silicide atop the raised extrinsic base that extends to the emitter region in a self-aligned manner. The silicide formation is incorporated into a BiCMOS process flow after the raised extrinsic base has been formed. The present invention also provides a heterojunction bipolar transistor having a raised extrinsic base and a silicide located atop the raised extrinsic base. The silicide atop the raised extrinsic base extends to the emitter in a self-aligned manner. The emitter is separated from the silicide by a spacer.Type: GrantFiled: September 21, 2005Date of Patent: June 24, 2008Assignee: International Business Machines CorporationInventors: Peter J. Geiss, Marwan H. Khater, Qizhi Liu, Randy W. Mann, Robert J. Purtell, BethAnn Rainey, Jae-Sung Rieh, Andreas D. Stricker
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Publication number: 20080138985Abstract: A method of forming silicide contacts for semiconductor devices includes subjecting a silicon containing semiconductor wafer to a degas treatment at an initial degas temperature of about 250 to about 400° C., transferring the semiconductor wafer from a degas chamber to a deposition chamber, depositing a nickel containing layer over the wafer following transfer of the wafer from the degas chamber to the deposition chamber, and annealing the semiconductor wafer so as to create silicide regions at portions on the wafer where nickel material is formed over silicon.Type: ApplicationFiled: December 6, 2006Publication date: June 12, 2008Applicants: INTERNATIONAL BUSINESS MACHINES CORPORATION, SAMSUNG ELECTRONICS CO., LTD.Inventors: Anita Madan, Robert J. Purtell, Keith Kwong Hon Wong, Jun-Keun Kwak
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Publication number: 20080124925Abstract: A method of forming silicide contacts for semiconductor devices includes subjecting a silicon containing semiconductor wafer to a degas treatment at a temperature of about 400° C., transferring the semiconductor wafer from a degas chamber to a deposition chamber, depositing a cobalt layer over the wafer at a point in time when the semiconductor wafer has cooled to temperature range of about 275-300° C., depositing a cap layer over the cobalt layer, and annealing the semiconductor wafer so as to create silicide contacts at portions on the wafer where cobalt is formed over silicon.Type: ApplicationFiled: September 25, 2006Publication date: May 29, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Anita Madan, Robert J. Purtell, Keith Kwong Hon Wong
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Patent number: 7344983Abstract: A cluster tool is provided for the implementing of a clustered and integrated surface pre-cleaning of the surface of semiconductor devices. More particularly, there is provided a cluster tool and a method of utilization thereof in an integrated semiconductor device surface pre-cleaning, which is directed towards a manufacturing aspect in which a chamber for performing a dry processing chemical oxide removal (COR) on the semiconductor device surface is clustered with other tools, such as a metal deposition tool for silicide or contact formation, including the provision of a vacuum transfer module in the cluster tool.Type: GrantFiled: March 18, 2005Date of Patent: March 18, 2008Assignee: International Business Machines CorporationInventors: Sadanand V. Deshpande, Ying Li, Kevin E. Mello, Renee T. Mo, Wesley C. Natzle, Kirk D. Peterson, Robert J. Purtell
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Patent number: 7320938Abstract: A method for reducing dendrite formation in a self-aligned, silicide process for a semiconductor device includes forming a silicide metal layer over a semiconductor substrate, the semiconductor device having one or more diffusion regions, one or more isolation areas and one or more gate structures formed thereon. The concentration of metal rich portions of the metal layer is reduced through the introduction of silicon thereto, and the semiconductor device is annealed.Type: GrantFiled: July 28, 2006Date of Patent: January 22, 2008Assignee: Internatioanl Business Machines CorporationInventors: Robert J. Purtell, Yun-Yu Wang, Keith Kwong Hon Wong
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Publication number: 20070269970Abstract: The present invention provides a semiconductor device comprising at least one field effect transistor (FET) having source and drain (S/D) metal silicide layers with intrinsic tensile or compressive stress. First, a metal layer containing a silicide metal M is formed over S/D regions of a FET, followed by a first annealing step to form S/D metal silicide layers that comprise a metal silicide of a first phase (MSix). A silicon nitride layer is then formed over the FET, followed by a second annealing step. During the second annealing step, the metal silicide is converted from the first phase (MSix) into a second phase (MSiy) with x<y. The metal silicide conversion causes either volumetric shrinkage or expansion in the S/D metal silicide layers of the FET, which in turn generates intrinsic tensile or compressive stress in the S/D metal silicide layers under confinement by the silicon nitride layer.Type: ApplicationFiled: May 19, 2006Publication date: November 22, 2007Applicant: International Business Machines CorporationInventors: Robert J. Purtell, Henry K. Utomo, Yun-Yu Wang, Haining S. Yang
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Patent number: 7208414Abstract: The present invention provides a method for enhancing uni-directional diffusion of a metal during silicidation by using a metal-containing silicon alloy in conjunction with a first anneal in which two distinct thermal cycles are performed. The first thermal cycle of the first anneal is performed at a temperature that is capable of enhancing the uni-directional diffusion of metal, e.g., Co and/or Ni, into a Si-containing layer. The first thermal cycle causes an amorphous metal-containing silicide to form. The second thermal cycle is performed at a temperature that converts the amorphous metal-containing silicide into a crystallized metal rich silicide that is substantially non-etchable as compared to the metal-containing silicon alloy layer or a pure metal-containing layer. Following the first anneal, a selective etch is performed to remove any unreacted metal-containing alloy layer from the structure.Type: GrantFiled: September 14, 2004Date of Patent: April 24, 2007Assignee: International Business Machines CorporationInventors: Anthony G. Domenicucci, Bradley P. Jones, Christian Lavoie, Robert J. Purtell, Yun Yu Wang, Kwong Hon Wong
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Patent number: 7129169Abstract: A method for forming a metal silicide contact for a semiconductor device includes forming a refractory metal layer over a substrate, including active and non-active area of said substrate, and forming a cap layer over the refractory metal layer. A counter tensile layer is formed over the cap layer, wherein the counter tensile layer is selected from a material such that an opposing directional stress is created between the counter tensile layer and the cap layer, with respect to a directional stress created between the refractory metal layer and the cap layer.Type: GrantFiled: May 12, 2004Date of Patent: October 31, 2006Assignee: International Business Machines CorporationInventors: Bradley P. Jones, Christian Lavoie, Robert J. Purtell, Yun-Yu Wang, Keith Kwong Hon Wong
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Patent number: 7109116Abstract: A method for reducing dendrite formation in a self-aligned, silicide process for a semiconductor device includes forming a silicide metal layer over a semiconductor substrate, the semiconductor device having one or more diffusion regions, one or more isolation areas and one or more gate structures formed thereon. The concentration of metal rich portions of the metal layer is reduced through the introduction of silicon thereto, and the semiconductor device is annealed.Type: GrantFiled: July 21, 2005Date of Patent: September 19, 2006Assignee: International Business Machines CorporationInventors: Robert J. Purtell, Yun-Yu Wang, Keith Kwong Hon Wong
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Patent number: 7081208Abstract: Methods are provided for making microfilters by subtractive techniques which remove a component or part of a filter material to form pores in the filter material and additive techniques which deposit a filter material onto a porous underlying substrate. All the methods employ a supercritical fluid or mixture which have very high solvency properties and low viscosity and CO2 is the preferred supercritical fluid.Type: GrantFiled: December 16, 2002Date of Patent: July 25, 2006Assignee: International Business Machines CorporationInventors: Kenneth J McCullough, Wayne M Moreau, Keith R Pope, Robert J Purtell, John P Simons, William A Syverson, Charles J Taft