Abstract: A communication interface device, system, method, and design structure for providing dynamic segment sparing and repair in a memory system. The communication interface device includes drive-side switching logic including driver multiplexers to select driver data for transmitting on link segments of a bus, and receive-side switching logic including receiver multiplexers to select received data from the link segments of the bus. The bus includes multiple data link segments, a clock link segment, and at least two spare link segments selectable by the drive-side switching logic and the receive-side switching logic to replace one or more of the data link segments and the clock link segment.

Abstract: A memory buffer, memory system and method for power-on initialization and test for a cascade interconnect memory system. The memory buffer includes a bus interface to links in a high-speed channel for communicating with a memory controller via a direct connection or via a cascade interconnection through an other memory buffer. The interface is operable in a SBC mode and a high-speed mode. The memory buffer also includes a field service interface (FSI) slave for receiving FSI signals from a FSI master. In addition, the memory buffer includes logic for executing a power-on and initialization training sequence initiated by the memory controller.

Abstract: A processing device, processing system, method, and design structure for an enhanced microprocessor interconnect with bit shadowing are provided. The processing device includes shadow selection logic to select a driver bit position as a shadowed driver value, and line drivers to transmit data for the selected driver bit position and the shadowed driver value on separate link segments of a bus. The processing device also includes shadow compare logic to compare a selected received value with a shadowed received value from the bus and identify a miscompare in response to a mismatch of the compare, and shadow counters to count a rate of the miscompare relative to a bus error rate over a period of time. A defective link segment is identified in response to the rate of the miscompare within a predefined threshold of the bus error rate.

Abstract: In one embodiment, a method is disclosed for timing responses to a plurality of memory requests. The method can include sending a plurality of memory requests to a plurality of in-line memory modules. The requests can be sent over a channel from a plurality of channels, where each channel can have a plurality of lanes. The method can receive responses to the plurality of memory requests over the channel and monitor the response to detect a timing relationship between at least two lanes from the plurality of lanes. In addition, the method can adjust a timing of a register loading and unloading sequence in response to the monitoring of multiple lanes and channels. Other embodiments are also disclosed.

Abstract: A method and apparatus for decoding a bitstream.

Abstract: Illumination of the interior product display space of a cold beverage merchandizer is enhanced by: a first reflector (90) disposed along a lower front region of the interior product display space at the front of the cabinet; a second reflector (92) disposed in the upper front region of the interior display space in operative association with a lamp (80); a third reflector (94) disposed in a side front region of the interior display space at a side and front of the cabinet; a fourth reflector (94) disposed in a side front region of the interior display space at a side and front of the cabinet opposite the third reflector, a fifth reflector (96) mounted to an interior facing surface of the door bounding the upper front region of the interior display space, and a sixth reflector (98) mounted to an interior facing surface of the door.

Abstract: A communications system that may include a transmitter, a receiver, connected over a communications network. A communication link on the communications network may transfer data between the transmitter and the receiver. The system may also include a logic unit to scramble a plurality of portions of the data at the transmitter based upon the communication link and may unscramble the plurality of portions of the data at the receiver. As a result, the logic unit may provide improved performance of the communication link and/or reduced power consumption of the communication link.

Abstract: Techniques for image edge filter processing are provided. Data samples surrounding vertical and horizontal edges of an image are acquired and iteratively processed. If the samples are associated with vertical edges, the data associated with the samples are transposed prior to applying a selected filter. The samples are stored in two buffers (one buffer for each unique side of an edge being processed) and selective filters applied thereon. Each sample set includes more than four samples of data. Once the filters are processed, the data in the buffers is written as portions of a modified image. If the samples were associated with vertical edges, then the data is re-transposed out of the buffers as it is written.

Abstract: A web application that facilitates the interaction between an educational institution and its members for the purpose of assisting a student in need is described. The application provides an accessible and user-friendly system for members of an educational institution to provide and gather information. The application may perform various functions that allow rapid and efficient transmission of information regarding a student in need so that those needs may be addressed.

Abstract: A mechanism for de-skewing and aligning data bits sent between two chips on an elastic interface. On the receiving end of an elastic interface, the eye of each data bit within a clock/data group is delayed by less than a bit time to align the eyes with the nearest clock edge of a received clock signal. In addition to aligning the eyes of the individual data bits with the nearest clock edge, IAP patterns are used to determine the amount of further delay needed to line up the individual data beats from each data bit. If the data beats for the data bits are not aligned, all but the slowest data beat are delayed to align the data beats for all bits. The additional delay is achieved using sample latches that result in a delayed signal with less jitter. As a result of having less jitter, the received, de-skewed, and aligned clock/data group can be forwarded to the operative portion of the receiving chip at an increased frequency.

Abstract: Methods and apparatus are disclosed for aligning received data bits in elastic interface systems. Depending upon which one of several alignment modes is selected, data bits can be loaded into FIFO latches on rising clock edges if the data was sent on rising clock edges, on falling clock edges if the data was sent on falling clock edges, or on the nearest clock edge if minimum latency is desired. Alternatively, data bits can be delayed by one or more bit times before loading into FIFO latches to reduce the elastic interface system's sensitivity to drift. The present invention permits a user to trade off factors related to for latency, drift, and skew by choosing among different alignment modes in an elastic interface system.

Abstract: A refrigerated display case has a body (72), at least one door (28; 32) coupled to the body, and an internal refrigerated compartment (24). The case includes a lighted sign apparatus (32) mounted to the body. The apparatus includes a bulb (64), a housing (60), and an at least partially transparent and/or translucent sign (62) carried by the housing. A number of extractable snap fasteners (120) extend through associated holes (150) in the housing and engage the sign to retain the sign in an installed condition.

Abstract: A method and apparatus for de-skewing and aligning digital data received over an elastic interface bus is disclosed. Upon receiving the data, it is sent through a programmable delay line. While in the programmable delay line, the data is sampled at three points within the data's eye pattern. The three sampling points are dynamically adjusted to maximize coverage of the data's eye pattern. During the adjustment of the sampling points to optimally cover the data's eye pattern, delayed data is sampled from an alternate sampler to prevent sampling from the functional sampler while the delay in the primary sampler is adjusted. Sampling from the alternate sampler while changing the sampling points of the functional sampler serves to reduce glitches that may occur by sampling the functional sampler while its sampling parameters are changed. The method and apparatus allow for alternate eye tracking and wrap around eye tracking.

Abstract: A method for evaluating an end-user's subjective assessment of streaming media quality includes obtaining reference data characterizing the media stream, and obtaining altered data characterizing the media stream after the media stream has traversed a channel that includes a network. An objective measure of the QOS of the media stream is then determined by comparing the reference data and the altered data.

Abstract: An interface alignment pattern for de-skewing data bits received on an elastic interface is disclosed. The interface alignment pattern is “busy” in that it has a high number of logic state transitions. The busy interface alignment pattern can be used for scrambling and unscrambling operational data. The interface alignment pattern has a unique timing sequence for determining the location of a data bit's first data beat.

Abstract: An interface alignment pattern for de-skewing data bits received on an elastic interface is disclosed. The interface alignment pattern is “busy” in that it has a high number of logic state transitions. The busy interface alignment pattern can be used for scrambling and unscrambling operational data. The interface alignment pattern has a unique timing sequence for determining the location of a data bit's first data beat.

Abstract: The display space of a multiple door display merchandiser is illuminated by one or more vertically extending lamps (80) disposed intermediate the vertical sides of an access opening to the display space. A multiple door assembly (44) covers the access opening. To enhance the illumination of the display space, a pair of vertically extending side reflectors (92) are provided, one extending alon one side of the access opening and the other extending along the other side of the access opening. An additional reflector may be mounted to an interior facing surface of the door along an upper front region of the door and/or a lower front region.

Abstract: A test pattern is loaded into a driver data shift register and sent from a driver chip to a receive chip over an M bit bus (0 to M?1). The test pattern is also generated at the receiver chip and used to compare to the actual received data. Failed compares are stored as logic ones in a bit error register (BER). A counter determines the number of failures by counting logic ones from the BER. The contents of a error position counter are latched in a error position latch and used to load a logic one (at the error bit position) into daisy chained self-heal control registers (SCR) in the receiver chip and the driver chip. The SCR sets a logic one into all bit positions after the error bit isolating the failed bit path and adding a spare bit path which is in bit position M.

Abstract: In one embodiment, a method is provided. The method comprises loading a processor with data from a source buffer, the data representing pixels from a first color space, and the pixels being ordered for display in a first orientation, transforming the data into data within a second color space, and storing the transformed data in a destination buffer in an order for display in a second orientation.