Patents by Inventor Robert J. Royer

Robert J. Royer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10345885
    Abstract: A method is described that includes choosing between one of two different ways to cause a memory device to enter a specific one of multiple lower power states that each comprise lower power consumption than a highest low power state. The method also includes asserting a first signal on a first signal line that is coupled to a power management controller of the memory device to indicate to the power management controller that a sideband channel of a memory bus that is coupled to the memory device is activated. The method also includes causing the memory device to enter the specific one of the multiple lower power states by also performing the chosen one of a) sending an in-band signal on said memory bus coupled with said asserting of said first signal, said in-band signal specifying the specific one of the multiple lower power states; or, b) sending a second signal on a second signal line that identifies the specific one of the multiple lower power states.
    Type: Grant
    Filed: September 27, 2016
    Date of Patent: July 9, 2019
    Assignee: Intel Corporation
    Inventors: Brian R. McFarlane, Robert J. Royer, Anoop Mukker, Eng Hun Ooi, Ritesh B. Trivedi
  • Publication number: 20180088658
    Abstract: A method is described that includes choosing between one of two different ways to cause a memory device to enter a specific one of multiple lower power states that each comprise lower power consumption than a highest low power state. The method also includes asserting a first signal on a first signal line that is coupled to a power management controller of the memory device to indicate to the power management controller that a sideband channel of a memory bus that is coupled to the memory device is activated. The method also includes causing the memory device to enter the specific one of the multiple lower power states by also performing the chosen one of a) sending an in-band signal on said memory bus coupled with said asserting of said first signal, said in-band signal specifying the specific one of the multiple lower power states; or, b) sending a second signal on a second signal line that identifies the specific one of the multiple lower power states.
    Type: Application
    Filed: September 27, 2016
    Publication date: March 29, 2018
    Inventors: Brian R. McFarlane, Robert J. Royer, Anoop Mukker, Eng Hun Ooi, Ritesh B. Trivedi
  • Publication number: 20170212832
    Abstract: In an embodiment, a memory interface may send an indication that a request is being sent. The indication may be sent to a non-volatile memory via a point-to-point bus between a memory interface and the non-volatile memory. The memory interface may send the request to the non-volatile memory via the bus. The request may include an address that may be used to identify a location for storing or reading data. The non-volatile memory may acquire the request from the bus and process the request. After processing the request, the non-volatile memory may send an indication to the memory interface that indicates the non-volatile memory has a response to send to the memory interface. The memory interface may grant access to the bus to the non-volatile memory. After being granted access to the bus, the non-volatile memory may send the response to the memory interface.
    Type: Application
    Filed: January 2, 2017
    Publication date: July 27, 2017
    Inventors: Eng Hun Ooi, Robert J. Royer, Michael W. Williams, Jeffrey R. Wilcox, Ritesh B. Trivedi, Blaise Fanning
  • Patent number: 7177983
    Abstract: In a Constant Access Time Bounded (CATB) cache, if a dirty line in a search group of the cache is selected for eviction from the cache, marking the dirty line as evicted, selecting a replacement line from a reserve, and inserting the replacement line into the search group.
    Type: Grant
    Filed: August 12, 2003
    Date of Patent: February 13, 2007
    Assignee: Intel Corporation
    Inventor: Robert J. Royer
  • Patent number: 6920533
    Abstract: A system and method to reduce the time for system initializations is disclosed. In accordance with the invention, data accessed during a system initialization is loaded into a non-volatile cache and is pinned to prevent eviction. By pinning data into the cache, the data required for system initialization is pre-loaded into the cache on a system reboot, thereby eliminating the need to access a disk.
    Type: Grant
    Filed: June 27, 2001
    Date of Patent: July 19, 2005
    Assignee: Intel Corporation
    Inventors: Richard L. Coulson, John I. Garney, Jeanna N. Matthews, Robert J. Royer
  • Publication number: 20040268026
    Abstract: An apparatus, as well as systems, methods, and articles can operate to record the address of write operations to a memory cached by a non-volatile cache prior to executing an operating system cache driver.
    Type: Application
    Filed: June 27, 2003
    Publication date: December 30, 2004
    Applicant: Intel Corporation
    Inventors: Robert J. Royer, Richard L. Coulson
  • Publication number: 20040225826
    Abstract: A nonvolatile memory module. The module includes a nonvolatile memory array and a connector allowing the array to make connection with a host system. A memory controller operates to either create an image of a nonvolatile intermediate memory in response to an imaging request or populate a nonvolatile intermediate memory in response to an installation request.
    Type: Application
    Filed: June 4, 2004
    Publication date: November 11, 2004
    Applicant: Intel Corporation (a Delaware corporation)
    Inventors: Robert J. Royer, John I. Garney
  • Publication number: 20040215923
    Abstract: In one embodiment of the present invention, a method includes observing disk requests for a drive associated with a memory device; and mapping the memory device based on observing the disk requests.
    Type: Application
    Filed: April 22, 2003
    Publication date: October 28, 2004
    Inventor: Robert J. Royer
  • Publication number: 20040073719
    Abstract: A method is described that involves sending a second command over a Serial ATA interface to a device before the device is able to execute a first command that was previously sent to the Serial ATA interface. In a further embodiment of the first command is tagged with a first reference number. In an even further embodiment of the method the second command is tagged with a second reference number.
    Type: Application
    Filed: September 30, 2002
    Publication date: April 15, 2004
    Inventors: Knut S. Grimsrud, Amber D. Huffman, Robert J. Royer
  • Publication number: 20030188123
    Abstract: Briefly, in accordance with an embodiment of the invention, a method to generate cache data is provided, wherein the method includes identifying access data transmitted from a storage device during execution of a predetermined software program and generating cache data using the identified access data.
    Type: Application
    Filed: April 1, 2002
    Publication date: October 2, 2003
    Inventors: Robert J. Royer, Knut S. Grimsrud
  • Publication number: 20030120868
    Abstract: Briefly, in accordance with an embodiment of the invention, a method and system to store cache metadata from a higher latency media in a lower latency media is provided.
    Type: Application
    Filed: December 21, 2001
    Publication date: June 26, 2003
    Inventors: Robert J. Royer, Jeanna N. Matthews
  • Publication number: 20030061428
    Abstract: A computing system having expansion modules. One of the expansion modules is identified as a master module. The other modules act as slaves to the master module. The central processing unit routes a task to either the master module for portioning out or to all of the expansion modules. The master module then receives completion signals from all of the active slave modules and then provides only one interrupt to the central processing unit for that task.
    Type: Application
    Filed: September 25, 2001
    Publication date: March 27, 2003
    Applicant: Intel Corporation
    Inventors: John I. Garney, Robert J. Royer
  • Publication number: 20030061436
    Abstract: A nonvolatile memory module. The module includes a nonvolatile memory array and a connector allowing the array to make connection with a host system. A memory controller operates to either create an image of a nonvolatile intermediate memory in response to an imaging request or populate a nonvolatile intermediate memory in response to an installation request.
    Type: Application
    Filed: September 25, 2001
    Publication date: March 27, 2003
    Applicant: Intel Corporation
    Inventors: Robert J. Royer, John I. Garney
  • Publication number: 20030005219
    Abstract: An apparatus and method to reduce the initialization time of a system is disclosed. In one embodiment, the invention stores metadata for data in a cache memory in a partitioned section of a non-volatile storage media. This allows multiple metadata entries to be read in one operation, thereby improving system performance.
    Type: Application
    Filed: June 29, 2001
    Publication date: January 2, 2003
    Inventors: Robert J. Royer, Knut S. Grimsrud, Richard L. Coulson
  • Publication number: 20030005223
    Abstract: A system and method to reduce the time for system initializations is disclosed. In accordance with the invention, data accessed during a system initialization is loaded into a non-volatile cache and is pinned to prevent eviction. By pinning data into the cache, the data required for system initialization is pre-loaded into the cache on a system reboot, thereby eliminating the need to access a disk.
    Type: Application
    Filed: June 27, 2001
    Publication date: January 2, 2003
    Inventors: Richard L. Coulson, John I. Garney, Jeanna N. Matthews, Robert J. Royer