Patents by Inventor ROBERT J. SANVILLE

ROBERT J. SANVILLE has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6618238
    Abstract: A novel capacitor foil and printed circuit board intermediate made using that foil are disclosed. The capacitor foil is a three-layer construction having a conductive layer, a partially-cured high dielectric constant layer, and a partially-cured bonding layer. The high dielectric constant and bonding layers are formed with epoxy or other polymer, however, the high dielectric constant layer is loaded with capacitive ceramic particles or pre-fired ceramic forming particles. The bonding layer may or may not be filled with ceramic particles or prefired ceramic-forming particles. The resulting capacitor foil may be applied to a laminate having copper patterns thereon to define a PCB intermediate containing at least one buried capacitor device. Multiple layers of capacitance material also can be used to increase the overall capacitance of the board.
    Type: Grant
    Filed: March 25, 1999
    Date of Patent: September 9, 2003
    Assignee: Polyclad Laminates, Inc.
    Inventor: Robert J. Sanville, Jr.
  • Publication number: 20020048137
    Abstract: A novel capacitor foil and printed circuit board intermediate made using that foil are disclosed. The capacitor foil is a two-layer construction having a conductive layer and a partially cured bonding layer having a high dielectric constant. The high dielectric bonding layer is formed with epoxy or other polymer and is loaded with capacitive ceramic particles or pre-fired ceramic forming particles. The resulting capacitor foil may be applied to a laminate having copper patterns thereon to define a PCB intermediate containing at least one buried capacitor device. Multiple layers of capacitance material also can be used to increase the overall capacitance of the board.
    Type: Application
    Filed: March 30, 2000
    Publication date: April 25, 2002
    Inventors: Thomas J. Williams, William D. Varnell, Robert J. Sanville
  • Publication number: 20010014004
    Abstract: A novel capacitor foil and printed circuit board intermediate made using that foil are disclosed. The capacitor foil is a three-layer construction having a conductive layer, a partially-cured high dielectric constant layer, and a partially-cured bonding layer. The high dielectric constant and bonding layers are formed with epoxy or other polymer, however, the high dielectric constant layer is loaded with capactive ceramic particles or pre-fired ceramic forming particles. The bonding layer may or may not be filled with ceramic particles or prefired ceramic-forming particles. The resulting capacitor foil may be applied to a laminate having copper patterns thereon to define a PCB intermediate containing at least one buried capacitor device. Multiple layers of capacitance material also can be used to increase the overall capacitance of the board.
    Type: Application
    Filed: March 25, 1999
    Publication date: August 16, 2001
    Inventor: ROBERT J. SANVILLE
  • Patent number: 5670250
    Abstract: This invention involves a prepreg composition and procedure for use in forming printed circuit boards with reduced and uniform dielectric constant, improved thermal expansion characteristics, and uniform appearance. The prepreg composite is a resin impregnated substrate and has a reduced dielectric constant as low as 3.5. It contains 5-30% by resin volume of hollow inorganic microsphere filler whose diameters are less than 40 micrometers, and the uniform distribution of the hollow inorganic microspheres is controlled by the presence of hydrophobic fumed silica or other similar flow modifier.
    Type: Grant
    Filed: May 16, 1995
    Date of Patent: September 23, 1997
    Assignee: Polyclad Laminates, Inc.
    Inventors: Robert J. Sanville, Jr., Carl P. Kernander