Patents by Inventor Robert J. Satriano

Robert J. Satriano has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7281946
    Abstract: A hermetically sealed package embodying the invention includes a base member having top and bottom surfaces. An electronic device having multiple electrodes is securely mounted on the top surface of the base member. The electrodes of the electronic device are made accessible to external circuits via wire connection to conducting leads disposed through pre-formed holes extending vertically from the top surface to the bottom surface of the base member. The conductive leads then extend horizontally along preformed grooves formed along the bottom surface of the base member. The holes with the leads passing though them are hermetically sealed. A portion of selected conductive leads extending above the top surface are selectively bonded to selected electrodes of the electronic device. A ceramic cap is mounted over and around the electronic device and the conductive leads and encompasses them. The cap has a bottom rim which fits into a preformed trench running along the outer periphery of the base member.
    Type: Grant
    Filed: February 15, 2006
    Date of Patent: October 16, 2007
    Assignee: American Berylia Corp.
    Inventors: Dino Nicoletta, Robert J. Satriano
  • Publication number: 20030068907
    Abstract: A package embodying the invention includes a base plate for receiving an electronic device having input/output points to be connected to an external system. Side walls mounted on the base plate enclose the electronic device. Selected side walls have a plurality of hermetically sealed openings through which are passed conductive leads which extend from within the package to outside the package for connecting the electronic device to the external system. A ceramic insert is mounted on the inside of at least one of the side walls. The ceramic insert has a first set of holes (terminals) for the direct contacting and connection thereto of selected conductive leads. The ceramic insert also has a second set of terminals whose layout is customized for optimally connecting selected ones of the second set of terminals to selected input/output points of the electronic device. The ceramic insert also includes a custom designed conductive pattern interconnecting selected ones of the first and second set of terminals.
    Type: Application
    Filed: May 30, 2002
    Publication date: April 10, 2003
    Inventors: Caesar Morte, Robert J. Satriano
  • Patent number: 5148264
    Abstract: A package for a device comprises a header having a substantially flat upper surface. An insulating disk is affixed to the upper surface of the header for having the device mounted thereon. A barrel having upper and lower portions of respectively greater and smaller diameters, and having a step between the diameters, has a lower edge thereof attached to the upper surface of the header so as to surround the disk. A ceramic lid in the upper portion of the barrel abuts the step is attached thereat.
    Type: Grant
    Filed: May 2, 1990
    Date of Patent: September 15, 1992
    Assignee: Harris Semiconductor Patents, Inc.
    Inventor: Robert J. Satriano
  • Patent number: 5105536
    Abstract: A hermetic, high current package for a semiconductor device includes wide flat leads which are bonded to the contact pads of the device and formed to extend through apertures in an insulating lid. The lid is sealed to a base and the apertures around the leads are sealed with solder to provide the hermetic package. This package limits lateral current flow in the contact pads of the semiconductor device to relatively low levels which ensure the integrity of the contact pads.
    Type: Grant
    Filed: April 23, 1991
    Date of Patent: April 21, 1992
    Assignee: General Electric Company
    Inventors: Constantine A. Neugebauer, Robert J. Satriano, James F. Burgess, Homer H. Glascock, II, Victor A. K. Temple, Donald L. Watrous
  • Patent number: 5097319
    Abstract: A cover for a semiconductor package consists of a plate of ceramic material, and has on its upper surface one or more openings for individually receiving terminals. Hollow truncated cylindrical-like cups each have a closed top portion with an opening for receiving an end of a threaded mounting stud, and an open bottom portion for mounting the cup over a terminal hole in the plate. The cups are each filled with a plurality of solder-coated pellets prior to mounting on the plate. The plate is then secured to the open top of the semiconductor package in a manner such that terminals protruding from the interior of the package pass through the holes in the plate and into the interior of the overlying cups, whereby the pellets provide electrical contact between the terminal and the end of the mounting stud protruding into the interior of the associated cup.
    Type: Grant
    Filed: March 21, 1991
    Date of Patent: March 17, 1992
    Assignee: Harris Corporation
    Inventor: Robert J. Satriano
  • Patent number: 5049973
    Abstract: A packaging assembly for electrical components includes a heat sink having a mounting surface upon which certain ones of the electrical components are mounted. An associated lead frame is rigidly secured to an edge of the heat sink, and one or more extended ends of selected leads thereof are formed into mounting pads positioned over the mounting surface of the heat sink for receiving other ones of the electrical components. Dielectric material is positioned between the mounting pads and the heat sink, for electrically isolating the electrical components mounted upon the mounting pads from one another and from electrical components mounted directly on the heat sink. The electrical components and proximate ends of the leads of the lead frame are electrically interconnected via electrical conductors, and the assembly is encapsulated with a plastic material about the heat sink and proximate ends of the lead frame, whereafter bridge elements between the leads of the lead frame are severed.
    Type: Grant
    Filed: June 26, 1990
    Date of Patent: September 17, 1991
    Assignee: Harris Semiconductor Patents, Inc.
    Inventors: Robert J. Satriano, Thomas R. McLean
  • Patent number: 5038197
    Abstract: An hermetically sealed package for a die comprised of a base plate, a side wall mounted on the brace plate, a printed circuit board connecting terminals on one side of the die to a first lead, connector clips connecting terminals on the other side of die to a bus having posts extending, wires connecting other terminals on the other side of the die to runners on the circuit board, leads respectively extending from each runner, a cover lid hermetically sealed to the side wall, the lid having openings hermetically sealed by insulators having slots through which the leads respectively extend in sealed relationship.
    Type: Grant
    Filed: June 26, 1990
    Date of Patent: August 6, 1991
    Assignee: Harris Semiconductor Patents, Inc.
    Inventor: Robert J. Satriano
  • Patent number: 5028987
    Abstract: A hermetic, high current package for a semiconductor device includes wide flat leads which are bonded to the contact pads of the device and formed to extend through apertures in an insulating lid. The lid is sealed to a base and the apertures around the leads are sealed with solder to provide the hermetic package. This package limits lateral current flow in the contact pads of the semiconductor device to relatively low levels which ensure the integrity of the contact pads.
    Type: Grant
    Filed: July 3, 1989
    Date of Patent: July 2, 1991
    Assignee: General Electric Company
    Inventors: Constantine A. Neugebauer, Robert J. Satriano, James F. Burgess, Homer H. Glascock, II, Victor A. K. Temple, Donald L. Watrous